Mark Kassab

	2011
24		Manish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab: A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores. ITC 2011: 1-9
23		Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski: EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. ITC 2011: 1-9
	2010
22		Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab: Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. ITC 2010: 114-123
21		Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer: Dynamic channel allocation for higher EDT compression in SoC designs. ITC 2010: 265-274
20		Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab: Low capture power at-speed test in EDT environment. ITC 2010: 714-723
19		Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab: At-speed scan test with low switching activity. VTS 2010: 177-182
	2009
18		Xijiang Lin, Mark Kassab: Test Generation for Designs with On-Chip Clock Generators. Asian Test Symposium 2009: 411-417
17		Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer: Low-Power Scan Operation in Test Compression Environment. IEEE Trans. on CAD of Integrated Circuits and Systems 28(11): 1742-1755 (2009)
	2008
16		Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer: Low Power Scan Shift and Capture in the EDT Environment. ITC 2008: 1-10
15		Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab: X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 147-159 (2008)
	2007
14		Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski: Test Generation in the Presence of Timing Exceptions and Constraints. DAC 2007: 688-693
13		Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai: X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Design & Test of Computers 24(5): 476-485 (2007)
	2006
12		Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab: X-Press Compactor for 1000x Reduction of Test Data. ITC 2006: 1-10
11		Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie: OCI: Open Compression Interface. ITC 2006: 1-4
	2004
10		Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski: Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. ITC 2004: 1285-1294
9		Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski: Realizing High Test Quality Goals with Smart Test Resource Usage. ITC 2004: 525-533
8		Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee: Embedded deterministic test. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 776-792 (2004)
	2003
7		Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski: Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. ITC 2003: 1211-1220
6		Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian: Embedded Deterministic Test for Low-Cost Manufacturing. IEEE Design & Test of Computers 20(5): 58-66 (2003)
	2002
5		Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian: Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC 2002: 301-310
	1999
4		Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski: Logic BIST for large industrial designs: real issues and case studies. ITC 1999: 358-367
	1998
3		Aiman H. El-Maleh, Mark Kassab, Janusz Rajski: A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. DAC 1998: 625-631
	1995
2		Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Software Accelerated Functional Fault Simulation for Data-Path Architectures. DAC 1995: 333-338
1		Mark Kassab, Janusz Rajski, Jerzy Tyszer: Hierarchical Functional-Fault Simulation for High-Level Synthesis. ITC 1995: 596-605

Coauthor Index

1	Ralf Arnold	[7]
2	Matthias Beck	[7]
3	Brady Benware	[10] [24]
4	Dwayne Burek	[11]
5	Wu-Tung Cheng	[12] [13] [15] [24]
6	Bruce Cory	[11]
7	Dariusz Czysz	[16] [17]
8	Avijit Dutta	[23] [24]
9	Geir Eide	[5]
10	Bill Eklow (William Eklow)	[9]
11	Aiman H. El-Maleh (Aiman El-Maleh)	[3]
12	Tony Fryars	[4]
13	Dhiraj Goswami	[14]
14	Xinli Gu	[9]
15	Abu S. M. Hassan	[4]
16	Andre Hertwig	[5]
17	Graham Hetherington	[4]
18	Jakub Janicki	[21] [23]
19	Rohit Kapur	[11]
20	Martin Keim	[10]
21	Brion L. Keller	[11]
22	Kee Sup Kim	[11]
23	Prabhu Krishnamurthy	[10]
24	Liyang Lai	[13]
25	Abby Lee	[9]
26	Xijiang Lin	[16] [17] [18] [20] [22]
27	Cam Lu	[10]
28	Robert Madge	[10]
29	Elham K. Moghaddam	[19] [20]
30	Richard Morren	[22]
31	Grzegorz Mrugalski	[5] [12] [13] [15] [16] [17] [21] [23]
32	Peter Muhmenthaler	[7]
33	Nilanjan Mukherjee	[2] [5] [6] [7] [8] [12] [13] [15] [20] [21] [23]
34	Benoit Nadeau-Dostie	[11]
35	Steven F. Oakland	[11]
36	Frank Poehl	[7]
37	Jun Qian	[5] [6]
38	Janusz Rajski	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [12] [13] [14] [15] [16] [17] [19] [20] [21] [23]
39	Sudhakar M. Reddy	[19] [20]
40	Manish Sharma	[13] [24]
41	John Van Slyke	[10]
42	Nagesh Tamarapalli	[4] [5] [6] [7]
43	Mick Tegethoff	[11]
44	Rob Thompson	[5]
45	Jan Arild Tofte	[9]
46	Kun-Han Tsai	[5] [9] [14]
47	Jerzy Tyszer	[1] [2] [5] [6] [8] [12] [13] [15] [16] [17] [21] [23]
48	Tom Waayers	[22]
49	Cyndee Wang	[9]

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