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| 2012 | ||
|---|---|---|
| 37 | Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky: Design for test and reliability in ultimate CMOS. DATE 2012: 677-682 | |
| 36 | Jaydeep Kulkarni, Bibiche M. Geuskens, Tanay Karnik, Muhammad M. Khellah, James Tschanz, Vivek De: Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM. ISSCC 2012: 234-236 | |
| 35 | Alice Wang, Ken Takeuchi, Tanay Karnik, Maysam Ghovanloo, Satoshi Shigematsu: Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference. J. Solid-State Circuits 47(1): 3-7 (2012) | |
| 2011 | ||
| 34 | Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar: 3DICs for tera-scale computing: a case study. ISPD 2011: 77-78 | |
| 33 | Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De: All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Trans. on Circuits and Systems 58-I(9): 2017-2025 (2011) | |
| 32 | Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar: Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration. IET Computers & Digital Techniques 5(3): 205-212 (2011) | |
| 31 | Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De: A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. J. Solid-State Circuits 46(1): 194-208 (2011) | |
| 30 | Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De: Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. J. Solid-State Circuits 46(4): 797-805 (2011) | |
| 2010 | ||
| 29 | James Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De: Resilient design in scaled CMOS for energy efficiency. ASP-DAC 2010: 625 | |
| 28 | Keith A. Bowman, Carlos Tokunaga, James Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De: Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. CICC 2010: 1-4 | |
| 27 | Bibiche M. Geuskens, Muhammad M. Khellah, Jaydeep Kulkarni, Tanay Karnik, Vivek De: Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays. CICC 2010: 1-4 | |
| 26 | Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De: Resilient microprocessor design for high performance & energy efficiency. ISLPED 2010: 355-356 | |
| 25 | James Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De: A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. ISSCC 2010: 282-283 | |
| 24 | Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep Kulkarni, James Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah: PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. ISSCC 2010: 352-353 | |
| 23 | Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya, Fatih Hamzaoglu, Muhammad M. Khellah, Tanay Karnik, Kevin Zhang: Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process. J. Solid-State Circuits 45(4): 751-758 (2010) | |
| 2009 | ||
| 22 | Keith A. Bowman, James Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar: Circuit techniques for dynamic variation tolerance. DAC 2009: 4-7 | |
| 21 | James Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik: Resilient circuits - Enabling energy-efficient performance and reliability. ICCAD 2009: 71-73 | |
| 20 | DiaaEldin Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek De: SRAM dynamic stability estimation using MPFP and its applications. Microelectronics Journal 40(11): 1523-1530 (2009) | |
| 2008 | ||
| 19 | DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De: Analytical Model for the Propagation Delay of Through Silicon Vias. ISQED 2008: 553-556 | |
| 18 | Hao Yu, Yiyu Shi, Lei He, Tanay Karnik: Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power. IEEE Trans. VLSI Syst. 16(12): 1609-1619 (2008) | |
| 17 | D. E. Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek K. De: Accurate Estimation of SRAM Dynamic Stability. IEEE Trans. VLSI Syst. 16(12): 1639-1647 (2008) | |
| 2007 | ||
| 16 | Peter Hazucha, Fabrice Paillet, Sung Tae Moon, David J. Rennie, Gerhard Schrom, Donald S. Gardner, Kenneth Ikeda, Gell Gellman, Tanay Karnik: Low Voltage Buffered Bandgap Reference. ISQED 2007: 93-97 | |
| 2006 | ||
| 15 | Tanay Karnik, Peter Hazucha, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner: High-frequency DC-DC conversion : fact or fiction. ISCAS 2006 | |
| 14 | Hao Yu, Yiyu Shi, Lei He, Tanay Karnik: Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. ISLPED 2006: 156-161 | |
| 13 | Changbo Long, Sasank Reddy, Sudhakar Pamarti, Lei He, Tanay Karnik: Power-efficient pulse width modulation DC/DC converters with zero voltage switching control. ISLPED 2006: 326-329 | |
| 12 | Ruchir Puri, Tanay Karnik, Rajiv V. Joshi: Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. VLSI Design 2006: 5-7 | |
| 2005 | ||
| 11 | Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang: Logic soft errors in sub-65nm technologies design and CAD challenges. DAC 2005: 2-4 | |
| 10 | Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi: Design of sub-90nm Circuits and Design Methodologies. ISQED 2005: 3-4 | |
| 2004 | ||
| 9 | Shekhar Borkar, Tanay Karnik, Vivek De: Design and reliability challenges in nanometer technologies. DAC 2004: 75 | |
| 8 | Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik: HiSIM: hierarchical interconnect-centric circuit simulator. ICCAD 2004: 489-496 | |
| 7 | Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva Narendra, Tanay Karnik, Vivek De: Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. ISLPED 2004: 263-268 | |
| 6 | Tanay Karnik, Peter Hazucha, Jagdish Patel: Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes. IEEE Trans. Dependable Sec. Comput. 1(2): 128-143 (2004) | |
| 2003 | ||
| 5 | Shekhar Borkar, Tanay Karnik, Siva Narendra, James Tschanz, Ali Keshavarzi, Vivek De: Parameter variations and impact on circuits and microarchitecture. DAC 2003: 338-342 | |
| 2002 | ||
| 4 | Tanay Karnik, Yibin Ye, James Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar: Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC 2002: 486-491 | |
| 3 | Tanay Karnik, Shekhar Borkar, Vivek De: Sub-90nm technologies: challenges and opportunities for CAD. ICCAD 2002: 203-206 | |
| 1995 | ||
| 2 | Tanay Karnik, Sung-Mo Kang: An empirical model for accurate estimation of routing delay in FPGAs. ICCAD 1995: 328-331 | |
| 1994 | ||
| 1 | Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab: Structural and behavioral synthesis for testability techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 777-785 (1994) | |
Colors in the list of coauthors
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