 | 2011 |
|---|
| 9 |       | Chandan Karfa,
Kunal Banerjee,
Dipankar Sarkar,
Chitta Mandal:
Equivalence Checking of Array-Intensive Programs.
ISVLSI 2011: 156-161 |
| 8 | | Chandan Karfa,
Chitta Mandal,
Dipankar Sarkar:
Verification of Register Transfer Level Low Power Transformations.
ISVLSI 2011: 313-314 |
| 2010 |
|---|
| 7 | | Chandan Karfa,
Dipankar Sarkar,
Chittaranjan A. Mandal:
Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques.
ISVLSI 2010: 428-433 |
| 6 | | Chandan Karfa,
Dipankar Sarkar,
Chitta Mandal:
Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 479-492 (2010) |
| 2008 |
|---|
| 5 | | Chandan Karfa,
Dipankar Sarkar,
Chitta Mandal,
P. Kumar:
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 556-569 (2008) |
| 2007 |
|---|
| 4 | | Chandan Karfa,
Dipankar Sarkar,
Chittaranjan A. Mandal,
Chris Reade:
Hand-in-hand verification of high-level synthesis.
ACM Great Lakes Symposium on VLSI 2007: 429-434 |
| 3 | | Chandan Karfa,
Chittaranjan A. Mandal,
Dipankar Sarkar,
Chris Reade:
Register Sharing Verification During Data-Path Synthesis.
ICCTA 2007: 135-140 |
| 2006 |
|---|
| 2 | | Chandan Karfa,
Chittaranjan A. Mandal,
Dipankar Sarkar,
S. R. Pentakota,
Chris Reade:
A Formal Verification Method of Scheduling in High-level Synthesis.
ISQED 2006: 71-78 |
| 1 | | Chandan Karfa,
Chittaranjan A. Mandal,
Dipankar Sarkar,
S. R. Pentakota,
Chris Reade:
Verification of Scheduling in High-level Synthesis.
ISVLSI 2006: 141-146 |
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