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Shrirang K. Karandikar Coauthor index pubzone.org

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DBLP keys2008
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShrirang K. Karandikar, Sachin S. Sapatnekar: Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 45-58 (2008)
2007
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud: Fast Electrical Correction Using Resizing and Buffering. ASP-DAC 2007: 553-558
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCharles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz: The nuts and bolts of physical synthesis. SLIP 2007: 89-94
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin-Ngai Sze: Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2009-2022 (2007)
2006
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze: Fast algorithms for slew constrained minimum cost buffering. DAC 2006: 308-313
2005
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShrirang K. Karandikar, Sachin S. Sapatnekar: Fast estimation of area-delay trade-offs in circuit sizing. ISCAS (4) 2005: 3575-3578
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShrirang K. Karandikar, Sachin S. Sapatnekar: Fast comparisons of circuit implementations. IEEE Trans. VLSI Syst. 13(12): 1329-1339 (2005)
2004
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShrirang K. Karandikar, Sachin S. Sapatnekar: Fast Comparisons of Circuit Implementations. DATE 2004: 910-915
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShrirang K. Karandikar, Sachin S. Sapatnekar: Logical effort based technology mapping. ICCAD 2004: 419-422
2003
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShrirang K. Karandikar, Sachin S. Sapatnekar: Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect. IEEE Trans. VLSI Syst. 11(6): 1094-1105 (2003)
2001
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShrirang K. Karandikar, Sachin S. Sapatnekar: Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect. DAC 2001: 377-382

Coauthor Index

1Charles J. Alpert [7] [8] [9] [10]
2Jiang Hu [7] [8]
3Shiyan Hu [7] [8]
4Zhuo Li [7] [8] [9]
5T. Mahmud [10]
6Gi-Joon Nam [9]
7Stephen T. Quay [9] [10]
8Haoxing Ren [9]
9Sachin S. Sapatnekar [1] [2] [3] [4] [5] [6] [11]
10Weiping Shi [7] [8]
11Chin-Ngai Sze [8]
12Cliff C. N. Sze (Chin Ngai Sze, Cliff N. Sze) [7] [9]
13Paul G. Villarrubia (Paul Villarrubia) [9] [10]
14Mehmet Can Yildiz [9] [10]

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