 | 2012 |
|---|
| 14 |       | Robert Czerwinski,
Dariusz Kania:
Area and speed oriented synthesis of FSMs for PAL-based CPLDs.
Microprocessors and Microsystems - Embedded Hardware Design 36(1): 45-61 (2012) |
| 2010 |
|---|
| 13 | | Adam Opara,
Dariusz Kania:
Decomposition-based logic synthesis for PAL-based CPLDs.
Applied Mathematics and Computer Science 20(2): 367-384 (2010) |
| 12 | | Dariusz Kania,
Adam Milik:
Logic synthesis based on decomposition for CPLDs.
Microprocessors and Microsystems - Embedded Hardware Design 34(1): 25-38 (2010) |
| 2009 |
|---|
| 11 | | Robert Czerwinski,
Dariusz Kania:
CPLD-oriented Synthesis of Finite State Machines.
DSD 2009: 521-528 |
| 10 | | Robert Czerwinski,
Dariusz Kania:
Synthesis of finite state machines for CPLDs.
Applied Mathematics and Computer Science 19(4): 647-659 (2009) |
| 2007 |
|---|
| 9 | | Dariusz Kania:
A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS.
ACM Great Lakes Symposium on VLSI 2007: 152-155 |
| 8 | | Dariusz Kania,
Józef Kulisz:
Logic synthesis for PAL-based CPLD-s based on two-stage decomposition.
Journal of Systems and Software 80(7): 1129-1141 (2007) |
| 2005 |
|---|
| 7 | | Dariusz Kania,
Józef Kulisz,
Adam Milik:
A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs.
DSD 2005: 114-121 |
| 6 | | Robert Czerwinski,
Dariusz Kania:
State Assignment for PAL-based CPLDs.
DSD 2005: 127-134 |
| 5 | | Dariusz Kania,
Adam Milik,
Józef Kulisz:
Decomposition of Multi-Output Functions for CPLDs.
DSD 2005: 442-449 |
| 2002 |
|---|
| 4 | | Dariusz Kania:
Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean Functions.
DATE 2002: 1087 |
| 2000 |
|---|
| 3 | | Dariusz Kania:
Decomposition-Based Synthesis and its Application in PAL-Oriented Technology Mapping.
EUROMICRO 2000: 1138-1145 |
| 2 | | Dariusz Kania:
A Technology Mapping Algorithm for PAL-Based Devices Using Multi-Output Function Graphs.
EUROMICRO 2000: 1146- |
| 1999 |
|---|
| 1 | | Dariusz Kania:
Two-Level Logic Synthesis on PAL-Based CPLD and FPGA Using Decomposition.
EUROMICRO 1999: 1278-1281 |
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