Yin-Shuin Kang

	2001
5		Chingwei Yeh, Yin-Shuin Kang: Cell-based layout techniques supporting gate-level voltage scaling for low power. IEEE Trans. VLSI Syst. 9(6): 983-986 (2001)
	2000
4		Chingwei Yeh, Yin-Shuin Kang: Cell-based layout techniques supporting gate-level voltage scaling for low power. IEEE Trans. VLSI Syst. 8(5): 629-633 (2000)
	1999
3		Ching-Wei Yeh, Min-Cheng Chang, Yin-Shuin Kang: Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven Designs. ARVLSI 1999: 155-169
2		Ching-Wei Yeh, Yin-Shuin Kang, Shan-Jih Shieh, Jinn-Shyan Wang: Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs. DAC 1999: 62-67
1		Chingwei Yeh, Yin-Shuin Kang: A simulated annealing based method supporting dual supply voltages in standard cell placement. ISCAS (1) 1999: 310-313

Coauthor Index

1	Min-Cheng Chang	[3]
2	Shan-Jih Shieh	[2]
3	Jinn-Shyan Wang	[2]
4	Chingwei Yeh (Ching-Wei Yeh)	[1] [2] [3] [4] [5]

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