Sung-Mo Kang

	2012
145		Sangho Shin, Kyungmin Kim, Sung-Mo Kang: Analysis of Passive Memristive Devices Array: Data-Dependent Statistical Model and Self-Adaptable Sense Resistance for RRAMs. Proceedings of the IEEE 100(6): 2021-2032 (2012)
	2011
144		Kyosun Kim, Sangho Shin, Sung-Mo Kang: Stateful logic pipeline architecture. ISCAS 2011: 2497-2500
143		Sangho Shin, Kyungmin Kim, Sung-Mo Kang: Complementary structure of memristive devices based passive memory arrays. ISCAS 2011: 321-324
142		Kyosun Kim, Sangho Shin, Sung-Mo Kang: Field Programmable Stateful Logic Array. IEEE Trans. on CAD of Integrated Circuits and Systems 30(12): 1800-1813 (2011)
141		Sangho Shin, Kyosun Kim, Sung-Mo Kang: Reconfigurable Stateful nor Gate for Large-Scale Logic-Array Integrations. IEEE Trans. on Circuits and Systems 58-II(7): 442-446 (2011)
140		Ji-Hye Bong, Kwan-Hee Jo, Kyeong-Sik Min, Sung-Mo Kang: Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits. J. Low Power Electronics 7(1): 87-95 (2011)
	2010
139		Sangho Shin, Kyungmin Kim, Sung-Mo Kang: Compact Models for Memristors Based on Charge-Flux Constitutive Relationships. IEEE Trans. on CAD of Integrated Circuits and Systems 29(4): 590-598 (2010)
138		Sangho Shin, Kyungmin Kim, Sung-Mo Kang: Data-Dependent Statistical Memory Model for Passive Array of Memristive Devices. IEEE Trans. on Circuits and Systems 57-II(12): 986-990 (2010)
	2009
137		Ji-Hye Bong, Yong-Jin Kwon, Kyeong-Sik Min, Sung-Mo Kang: New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs. ISQED 2009: 459-464
	2008
136		Sangho Shin, Seokoh Yun, Sanghyun Cho, Jongmoon Kim, Minseok Kang, Wonkab Oh, Sung-Mo Kang: 0.18um CMOS integrated chipset for 5.8GHz DSRC systems with +10dBm output power. ISCAS 2008: 1958-1961
135		Jae-Jin Jung, Kwang-Hyun Baek, Shin-Il Lim, Suki Kim, Sung-Mo Kang: Design of a 6 bit 1.25 GS/s DAC for WPAN. ISCAS 2008: 2262-2265
134		Yong Sin Kim, Sung-Mo Kang: A 8-Gb/s/pin current mode multi-level simultaneous bidirectional I/O. ISCAS 2008: 3069-3072
133		Je-Hyoung Park, Ali Shakouri, Sung-Mo Kang: Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages. ISQED 2008: 600-603
	2007
132		Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu: Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. ICCD 2007: 71-77
131		Yong Sin Kim, Sung-Mo Kang: Programmable High Speed Multi-Level Simultaneous Bidirectional I/O. ISQED 2007: 416-419
	2006
130		Sangho Shin, Kwyro Lee, Sung-Mo Kang: 2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop. ISCAS 2006
129		Yong Sin Kim, Sangho Shin, Sung-Mo Kang: A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration. ISCAS 2006
128		Sangho Shin, Kwyro Lee, Sung-Mo Kang: Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors. ISCAS 2006
	2005
127		Ge Yang, Yong Sin Kim, Sung-Mo Kang: Current mode multi-level simultaneous bidirectional I/O scheme for chip-to-chip communications. ISCAS (6) 2005: 5493-5496
126		Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang: A 32-bit carry lookahead adder using dual-path all-N logic. IEEE Trans. VLSI Syst. 13(8): 992-996 (2005)
	2004
125		Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang: A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic. ISCAS (2) 2004: 781-784
124		Ge Yang, Zhongda Wang, Sung-Mo Kang: Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates. ISQED 2004: 421-424
123		Ge Yang, Zhongda Wang, Sung-Mo Kang: Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies. VLSI Design 2004: 222-227
	2003
122		Kwang-Hyun Baek, Myung-Jun Choe, Edward Merlo, Sung-Mo Kang: 1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs. ISCAS (1) 2003: 901-904
121		Sung-Mo Kang: Elements of low power design for integrated systems. ISLPED 2003: 205-210
120		Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang: An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters. ISVLSI 2003: 80-86
119		Yong Sin Kim, Soo Hwan Kim, Kwang-Hyun Baek, Suki Kim, Sung-Mo Kang: Multiple Trigonometric Approximation of Sine-Amplitude with Small ROM Size for Direct Digital Frequency Synthesizers. VLSI Design 2003: 261-
118		Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang: Minimum delay optimization for domino circuits - a coupling-aware approach. ACM Trans. Design Autom. Electr. Syst. 8(2): 202-213 (2003)
117		Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang: Energy-efficient skewed static logic with dual Vt: design and synthesis. IEEE Trans. VLSI Syst. 11(1): 64-70 (2003)
116		Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang: Noise-aware interconnect power optimization in domino logic synthesis. IEEE Trans. VLSI Syst. 11(1): 79-89 (2003)
115		Jaesik Lee, Ki-Wook Kim, Yoonjong Huh, Peter Bendix, Sung-Mo Kang: Chip-level charged-device modeling and simulation in CMOS integrated circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 67-81 (2003)
114		Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang: Timing constraints for domino logic gates with timing-dependent keepers. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 96-103 (2003)
	2002
113		Robert K. Grube, Qi Wang, Sung-Mo Kang: Design limitations in deep sub-0.1µm CMOS SRAM. ACM Great Lakes Symposium on VLSI 2002: 94-97
112		Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang: Low-swing clock domino logic incorporating dual supply and dual threshold voltages. DAC 2002: 467-472
111		Jaesik Lee, Ki-Wook Kim, Sung-Mo Kang: VeriCDF: a new verification methodology for charged device failures. DAC 2002: 874-879
110		Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang: Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. DATE 2002: 260-265
109		Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang: A low-voltage high-speed BiCMOS current switch with enhanced-spectral performance. ISCAS (5) 2002: 53-56
108		Sung-Mo Kang: On-chip thermal engineering for peta-scale integration. ISPD 2002: 76-76
107		Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang: Optimal Timing for Skew-Tolerant High-Speed Domino Logic. ISVLSI 2002: 41-46
106		Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu: Logic transformation for low-power synthesis. ACM Trans. Design Autom. Electr. Syst. 7(2): 265-283 (2002)
105		Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang: Noise constrained transistor sizing and power optimization for dual Vst domino logic. IEEE Trans. VLSI Syst. 10(5): 532-541 (2002)
104		Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang: Domino logic synthesis based on implication graph. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 232-240 (2002)
	2001
103		Kaushik Roy, Sung-Mo Kang, Cheng-Kok Koh: Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001 ACM 2001
102		Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang: Transistor sizing for reliable domino logic design in dual threshold voltage technologies. ACM Great Lakes Symposium on VLSI 2001: 133-138
101		Edward Ahn, Seung-Moon Yoo, Sung-Mo Kang: Effective algorithms for cache-level compression. ACM Great Lakes Symposium on VLSI 2001: 89-92
100		Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang: 2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test. ACM Great Lakes Symposium on VLSI 2001: 93-96
99		Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang: Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. DAC 2001: 732-737
98		Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang: Understanding and Addressing the Noise Induced By Electrostatic Discharge in Multiple Power Supply Systems. ICCD 2001: 406-414
97		Jinghong Chen, Sung-Mo Kang: Model-order reduction of nonlinear MEMS devices through arclength-based Karhunen-Loeve decomposition. ISCAS (3) 2001: 457-460
96		Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang: Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. ISCAS (4) 2001: 1-4
95		Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang: Skew-tolerant high-speed (STHS) domino logic. ISCAS (4) 2001: 154-157
94		Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang: Noise constrained power optimization for dual VT domino logic. ISCAS (4) 2001: 158-161
93		Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang: Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology. ISCAS (4) 2001: 746-749
92		Chulwoo Kim, Sung-Mo Kang: A low-power reduced swing single clock flip-flop. ISCAS (4) 2001: 806-809
91		Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang: Energy-efficient skewed static logic design with dual Vt. ISCAS (4) 2001: 882-885
90		Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang: New current-mode sense amplifiers for high density DRAM and PIM architectures. ISCAS (4) 2001: 938-941
89		Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang: Coupling-aware minimum delay optimization for domino logic circuits. ISCAS (5) 2001: 371-374
88		Q. Li, Sung-Mo Kang: Trapezoid-to-simple polygon recomposition for resistance extraction. ISCAS (5) 2001: 495-498
87		Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang: ESD design rule checker. ISCAS (5) 2001: 499-502
86		Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang: Full chip ESD design rule checking. ISCAS (5) 2001: 503-506
85		Ki-Wook Kim, Sung-Mo Kang: Crosstalk noise minimization in domino logic design. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1091-1100 (2001)
	2000
84		Qiao Li, Sung-Mo Kang: Technology independent arbitrary device extractor. ACM Great Lakes Symposium on VLSI 2000: 143-146
83		Qiao Li, Sung-Mo Kang: Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching. ACM Great Lakes Symposium on VLSI 2000: 183-188
82		Ki-Wook Kim, Unni Narayanan, Sung-Mo Kang: Domino logic synthesis minimizing crosstalk. DAC 2000: 280-285
81		N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang: When bad things happen to good chips (panel session). DAC 2000: 736-737
80		Ching-Han Tsai, Sung-Mo Kang: Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction. DAC 2000: 750-755
79		Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang: Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. ICCAD 2000: 318-321
78		Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang: High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology. ICCD 2000: 59-64
77		Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang: Noise-aware power optimization for on-chip interconnect. ISLPED 2000: 108-113
76		Jay R. Moorman, John W. Lockwood, Sung-Mo Kang: Real-time prioritized call admission control in a base station scheduler. WOWMOM 2000: 28-37
75		Yi-Kan Cheng, Sung-Mo Kang: A temperature-aware simulation environment for reliable ULSI chipdesign. IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1211-1220 (2000)
74		Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang: Interconnect thermal modeling for accurate simulation of circuittiming and reliability. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 197-205 (2000)
73		Ching-Han Tsai, Sung-Mo Kang: Cell-level placement for improving substrate thermal distribution. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 253-266 (2000)
	1999
72		Tong Li, Ching-Han Tsai, Elyse Rosenbaum, Sung-Mo Kang: Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation. DAC 1999: 549-554
71		Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu: Logic Transformation for Low Power Synthesis. DATE 1999: 158-162
70		Seung-Moon Yoo, Sung-Mo Kang: No-Race Charge-Recycling Differential Logic (NCDL). Great Lakes Symposium on VLSI 1999: 202-205
69		Chulwoo Kim, Seung-Moon Yoo, Sung-Mo Kang: NMOS Energy Recovery Logic. Great Lakes Symposium on VLSI 1999: 310-313
68		Ki-Wook Kim, C. L. Liu, Sung-Mo Kang: Implication graph based domino logic synthesis. ICCAD 1999: 111-114
67		Yi-Kan Cheng, Sung-Mo Kang: An efficient method for hot-spot identification in ULSI circuits. ICCAD 1999: 124-127
66		Seung-Moon Yoo, Sung-Mo Kang: CMOS Pass-gate No-race Charge-recycling Logic (CPNCL). ISCAS (1) 1999: 226-229
65		Jinghong Chen, Sung-Mo Kang: A mixed frequency-time approach for quasi-periodic steady-state simulation of multi-level modeled circuits. ISCAS (6) 1999: 194-197
64		Yi-Kan Cheng, Sung-Mo Kang: Temperature-driven power and timing analysis for CMOS ULSI circuits. ISCAS (6) 1999: 214-217
63		Ching-Han Tsai, Sung-Mo Kang: Macrocell placement with temperature profile optimization. ISCAS (6) 1999: 390-393
62		Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang: Interconnect thermal modeling for determining design limits on current density. ISPD 1999: 172-178
61		Ching-Han Tsai, Sung-Mo Kang: Standard cell placement for even on-chip thermal distribution. ISPD 1999: 179-184
	1998
60		Tong Li, Sung-Mo Kang: Layout Extraction and Verification Methodology CMOS I/O Circuits. DAC 1998: 291-296
59		Tong Li, Ching-Han Tsai, Sung-Mo Kang: Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress. ICCAD 1998: 6-11
58		Haoran Duan, John W. Lockwood, Sung-Mo Kang: Matrix unit cell scheduler (MUCS) for input-buffered ATM switches. IEEE Communications Letters 2(1): 20-23 (1998)
57		Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang: Statistical estimation of average power dissipation using nonparametric techniques. IEEE Trans. VLSI Syst. 6(1): 65-73 (1998)
56		Yi-Kan Cheng, Prasun Raha, Chin-Chi Teng, Elyse Rosenbaum, Sung-Mo Kang: ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 668-681 (1998)
	1997
55		Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang: Statistical Estimation of Average Power Dissipation in Sequential Circuits. DAC 1997: 377-382
54		Jaewon Kim, Sung-Mo Kang: An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design. DAC 1997: 456-459
53		Sueng-Yong Park, Vaduvur Bharghavan, Sung-Mo Kang: Data Link Level Support for Handoff in Wireless ATM Network. ICC (2) 1997: 765-769
52		Ashfaq Hossain, Sung-Mo Kang, Bob Horst: Performance Comparison of Video Transport over ATM and ServerNet Interconnects. ICMCS 1997: 612-613
51		Haoran Duan, John W. Lockwood, Sung-Mo Kang, J. D. Will: A High-Performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM Switches. INFOCOM 1997: 20-28
50		Li-Pen Yuan, Sung-Mo Kang: A sequential procedure for average power analysis of sequential circuits. ISLPED 1997: 231-234
49		Brent K. Whitlock, Petar K. Pepeljugoski, Daniel M. Kuchta, John D. Crow, Sung-Mo Kang: Computer Modeling and Simulation of the Optoelectronic Technology Consortium (OETC) Optical Bus. IEEE Journal on Selected Areas in Communications 15(4): 717-730 (1997)
48		Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang: iTEM: a temperature-dependent electromigration reliability diagnosis tool. IEEE Trans. on CAD of Integrated Circuits and Systems 16(8): 882-893 (1997)
	1996
47		Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang: iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips. DAC 1996: 548-551
46		Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang: Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects. DAC 1996: 752-757
45		Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang: Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques. ISLPED 1996: 73-78
44		Anthony M. Hill, Sung-Mo Kang: Determining accuracy bounds for simulation-based switching activity estimation. IEEE Trans. on CAD of Integrated Circuits and Systems 15(6): 611-618 (1996)
43		Jaewon Kim, Sung-Mo Kang: A new triple-layer OTC channel router. IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1059-1070 (1996)
	1995
42		Tanay Karnik, Sung-Mo Kang: An empirical model for accurate estimation of routing delay in FPGAs. ICCAD 1995: 328-331
41		Chin-Chi Teng, Anthony M. Hill, Sung-Mo Kang: Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits. ICCAD 1995: 366-370
40		Jaewon Kim, Sung-Mo Kang: A timing-driven data path layout synthesis with integer programming. ICCAD 1995: 716-719
39		Yi-Kan Cheng, Sung-Mo Kang: Chip-Level Thermal Simulator to Predict VLSI Chip Temperature. ISCAS 1995: 1392-1395
38		Elizabeth J. Brauer, Sung-Mo Kang: An Analytic Method to Calculate Emitter Follower Delay Using Trial Functions in Coupled Node Equations. ISCAS 1995: 1580-1583
37		Myong H. Cynn, Sung-Mo Kang: Incremental Node Extraction Algorithms for Incremental Layout System. ISCAS 1995: 1691-1694
36		Elizabeth J. Brauer, Sung-Mo Kang: Estimating Node Voltages in Bipolar Circuits Using Linear Programming. ISCAS 1995: 901-903
35		Anthony M. Hill, Sung-Mo Kang: Determining accuracy bounds for simulation-based switching activity estimation. ISLPD 1995: 215-220
34		Elizabeth J. Brauer, Sung-Mo Kang: An algorithm for functional verification of digital ECL circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1546-1556 (1995)
33		Abhijit Dharchoudhury, Sung-Mo Kang: Worst-case analysis and optimization of VLSI circuit performances. IEEE Trans. on CAD of Integrated Circuits and Systems 14(4): 481-492 (1995)
32		Mysore Sriram, Sung-Mo Kang: Efficient approximation of the time domain response of lossy coupled transmission line trees. IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 1013-1024 (1995)
	1994
31		Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee: Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics. ICCAD 1994: 190-194
30		Abhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel: Fast timing simulation of transient faults in digital circuits. ICCAD 1994: 719-722
29		Eby G. Friedman, Sung-Mo Kang, Eric A. Vittoz, David J. Allstot, Erik P. Harris, Ran-Hong Yan: Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS. ISCAS 1994: 1-6
28		Jaewon Kim, Sung-Mo Kang, Sachin S. Sapatnekar: High Performance CMOS Macromodule Layout Synthesis. ISCAS 1994: 179-182
27		Anthony M. Hill, Sung-Mo Kang: Genetic Algorithm Based Design Optimization Of CMOS VLSI Circuits. PPSN 1994: 546-555
26		Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang: Convexity-based algorithms for design centering. IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1536-1549 (1994)
25		Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury: Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices. IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 482-493 (1994)
	1993
24		Abhijit Dharchoudhury, Sung-Mo Kang: Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits. DAC 1993: 154-158
23		Mysore Sriram, Sung-Mo Kang: Fast Approximation of the Transient Response of Lossy Transmision Line Trees. DAC 1993: 691-696
22		Carlos H. Díaz, Charvaka Duvvury, Sung-Mo Kang: Thermal Failure Simulation for Electrical Overstress in Semiconductor Devices. ISCAS 1993: 1389-1392
21		Elizabeth J. Brauer, Sung-Mo Kang: Functional Verification of ECL Circuits Including Voltage Regulators. ISCAS 1993: 1710-1713
20		Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang: Feasible Region Approximation Using Convex Polytopes. ISCAS 1993: 1786-1789
19		Jun Dong Cho, Majid Sarrafzadeh, Mysore Sriram, Sung-Mo Kang: High-Performance MCM Routing. IEEE Design & Test of Computers 10(4): 27-37 (1993)
18		Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang: An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 12(11): 1621-1634 (1993)
17		Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang: ILLIADS: a fast timing and reliability simulator for digital MOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(9): 1387-1402 (1993)
	1992
16		Abhijit Dharchoudhury, Sung-Mo Kang: An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits. DAC 1992: 704-709
15		Mysore Sriram, Sung-Mo Kang: Detailed layer assignment for MCM routing. ICCAD 1992: 386-389
14		Carlos H. Díaz, Sung-Mo Kang: New algorithms for circuit simulation of device breakdown. IEEE Trans. on CAD of Integrated Circuits and Systems 11(11): 1344-1354 (1992)
13		Richard W. Thaik, Ngee Lek, Sung-Mo Kang: A new global router using zero-one integer linear programming techniques for sea-of-gates and custom logic arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 11(12): 1479-1494 (1992)
12		Yusuf Leblebici, Sung-Mo Kang: Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation. IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 235-246 (1992)
11		Yung-Ho Shih, Sung-Mo Kang: Analytic transient solution of general MOS circuit primitives. IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 719-731 (1992)
	1991
10		Yung-Ho Shih, Sung-Mo Kang: ILLIADS: A New Fast MOS Timing Simulator Using Direct Equation-Solving Approach. DAC 1991: 20-25
9		Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang: New Simulation Methods for MOS VLSI Timing and Reliability. ICCAD 1991: 162-165
8		Carlos H. Díaz, Sung-Mo Kang, Yusuf Leblebici: An accurate analytical delay model for BiCMOS driver circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 577-588 (1991)
7		H. Y. Chen, Sung-Mo Kang: A new circuit optimization technique for high performance CMOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 670-677 (1991)
	1990
6		Yusuf Leblebici, Sung-Mo Kang: An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis. ICCAD 1990: 400-403
	1987
5		D. K. Hwang, W. Kent Fuchs, Sung-Mo Kang: An Efficient Approach to Gate Matrix Layout. IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 802-809 (1987)
4		Sung-Mo Kang: Metal--Metal Matrix (M /sup 3/) for High-Speed MOS VLSI Layout. IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 886-891 (1987)
3		Tat-Kwan Yu, Sung-Mo Kang, I. N. Haji, Timothy N. Trick: Statistical Performance Modeling and Parametric Yield Estimation of MOS VLSI. IEEE Trans. on CAD of Integrated Circuits and Systems 6(6): 1013-1022 (1987)
	1983
2		Sung-Mo Kang, Robert H. Krambeck, Hung-Fai Stephen Law, Alexander D. Lopez: Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design. IEEE Trans. on CAD of Integrated Circuits and Systems 2(1): 18-29 (1983)
	1982
1		Sung-Mo Kang, Robert H. Krambeck, Hung-Fai Stephen Law: Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design. DAC 1982: 170-174

Coauthor Index

1	Edward Ahn	[101]
2	David J. Allstot	[29]
3	Kwang-Hyun Baek	[78] [79] [90] [109] [119] [120] [122] [125] [126] [135]
4	Peter Bendix	[86] [87] [93] [98] [115]
5	Vaduvur Bharghavan	[53]
6	Ji-Hye Bong	[137] [140]
7	Elizabeth J. Brauer	[21] [34] [36] [38]
8	Hungse Cha	[30]
9	Danqing Chen	[62] [74]
10	H. Y. Chen	[7]
11	Jau-Wen Chen	[86] [87]
12	Jinghong Chen	[65] [97]
13	Yi-Kan Cheng	[39] [46] [47] [48] [56] [64] [67] [75]
14	Jun Dong Cho	[19]
15	Sanghyun Cho	[136]
16	Myung-Jun Choe	[109] [120] [122]
17	John D. Crow	[49]
18	Myong H. Cynn	[37]
19	Abhijit Dharchoudhury	[16] [24] [30] [31] [33] [47]
20	Carlos H. Díaz	[8] [14] [22] [25]
21	Haoran Duan	[51] [58]
22	Charvaka Duvvury	[22] [25]
23	Eby G. Friedman	[29]
24	W. Kent Fuchs	[5]
25	Robert K. Grube	[113]
26	I. N. Haji	[3]
27	Erik P. Harris	[29]
28	Anthony M. Hill	[27] [35] [41] [44]
29	Ray Hokinson	[81]
30	Bob Horst	[52]
31	Ashfaq Hossain	[52]
32	Yoonjong Huh	[86] [87] [93] [98] [115]
33	D. K. Hwang	[5]
34	TingTing Hwang	[71] [106]
35	Kwan-Hee Jo	[140]
36	Jae-Jin Jung	[135]
37	Seong-Ook Jung	[77] [89] [90] [94] [95] [96] [99] [100] [102] [105] [107] [110] [112] [114] [116] [118] [125] [126]
38	Andrew B. Kahng	[132]
39	Minseok Kang	[136]
40	Wonjae L. Kang	[81]
41	Tanay Karnik	[42]
42	Chulwoo Kim	[69] [78] [90] [91] [92] [117]
43	Jaewon Kim	[28] [40] [43] [54]
44	Jongmoon Kim	[136]
45	K. H. (Kane) Kim (K. H. Kim, Kane Kim, Kwang-Hae (Kane) Kim)	[31]
46	Ki-Wook Kim	[68] [71] [77] [79] [82] [85] [89] [91] [94] [95] [99] [102] [104] [105] [106] [107] [110] [111] [112] [114] [115] [116] [117] [118]
47	Kyosun Kim	[141] [142] [144]
48	Kyungmin Kim	[138] [139] [143] [145]
49	Soo Hwan Kim	[119] [125] [126]
50	Suki Kim	[119] [125] [126] [135]
51	Taewhan Kim	[104] [106] [118]
52	Yong Sin Kim	[119] [127] [129] [131] [134]
53	Cheng-Kok Koh	[103]
54	Robert H. Krambeck	[1] [2]
55	Daniel M. Kuchta	[49]
56	Yong-Jin Kwon	[137]
57	Hung-Fai Stephen Law	[1] [2]
58	Yusuf Leblebici	[6] [8] [9] [12] [17]
59	Jaesik Lee	[78] [93] [98] [111] [115]
60	Kwyro Lee	[128] [130]
61	S. H. Lee	[31]
62	Ngee Lek	[13]
63	Erhong Li	[62] [74]
64	Q. Li	[86] [87] [88]
65	Qiao Li	[83] [84]
66	Tong Li	[59] [60] [72]
67	Wei Li	[132]
68	Shin-Il Lim	[135]
69	Bao Liu	[132]
70	C. L. Liu (Chung Laung (Dave) Liu)	[68] [71] [77] [79] [99] [104] [106] [116]
71	John W. Lockwood	[51] [58] [76]
72	Alexander D. Lopez	[2]
73	Eric Martina	[78]
74	Edward Merlo	[122]
75	Kyeong-Sik Min	[137] [140]
76	Jay R. Moorman	[76]
77	N. S. Nagaraj	[81]
78	Unni Narayanan	[77] [82] [116]
79	Sani R. Nassif	[81]
80	Wonkab Oh (Wonkap Oh)	[136]
81	David Overhauser	[81]
82	Je-Hyoung Park	[133]
83	Sueng-Yong Park	[53]
84	Janak H. Patel	[30]
85	Petar K. Pepeljugoski	[49]
86	Prasun Raha	[56]
87	Vasant B. Rao	[18]
88	Elyse Rosenbaum	[46] [47] [48] [56] [62] [72] [74]
89	Kaushik Roy	[103]
90	Sachin S. Sapatnekar	[18] [20] [26] [28]
91	Majid Sarrafzadeh	[19]
92	Prashant Saxena	[99]
93	Ali Shakouri	[133]
94	Naresh R. Shanbhag	[79]
95	Yung-Ho Shih	[9] [10] [11] [17]
96	Sangho Shin	[128] [129] [130] [136] [138] [139] [141] [142] [143] [144] [145]
97	Mysore Sriram	[15] [19] [23] [32]
98	Andrzej J. Strojwas (Andreas J. Strojwas)	[81]
99	Chin-Chi Teng	[41] [45] [46] [47] [48] [55] [56] [57]
100	Richard W. Thaik	[13]
101	Timothy N. Trick	[3]
102	Ching-Han Tsai	[59] [61] [63] [72] [73] [80]
103	Pravin M. Vaidya	[18] [20] [26]
104	Eric A. Vittoz	[29]
105	Qi Wang	[113]
106	Zhongda Wang	[123] [124]
107	Brent K. Whitlock	[49]
108	J. D. Will	[51]
109	Ran-Hong Yan	[29]
110	Ge Yang	[123] [124] [125] [126] [127]
111	Seung-Moon Yoo	[66] [69] [70] [90] [95] [96] [100] [101]
112	Tak Young	[81]
113	Tat-Kwan Yu	[3]
114	Li-Pen Yuan	[45] [50] [55] [57]
115	Seokoh Yun	[136]

Colors in the list of coauthors

Last update Sat Jun 2 20:57:36 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page