 | 2011 |
|---|
| 10 |       | Jongpil Jung,
Kyungsu Kang,
Chong-Min Kyung:
Design and management of 3D-stacked NUCA cache for chip multiprocessors.
ACM Great Lakes Symposium on VLSI 2011: 91-96 |
| 9 | | Woojin Yun,
Kyungsu Kang,
Chong-Min Kyung:
Thermal-aware energy minimization of 3D-stacked L3 cache with error rate limitation.
ISCAS 2011: 1672-1675 |
| 8 | | Kyungsu Kang,
Jongpil Jung,
Sungjoo Yoo,
Chong-Min Kyung:
Maximizing throughput of temperature-constrained multi-core systems with 3D-stacked cache memory.
ISQED 2011: 577-582 |
| 7 | | Asim Khan,
Kyungsu Kang,
Chong-Min Kyung:
Exploiting maximum throughput in 3D multicore architectures with stacked NUCA cache.
VLSI-SoC 2011: 130-135 |
| 6 | | Kyungsu Kang,
Jungsoo Kim,
Sungjoo Yoo,
Chong-Min Kyung:
Runtime Power Management of 3-D Multi-Core Architectures Under Peak Power and Temperature Constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 30(6): 905-918 (2011) |
| 2010 |
|---|
| 5 | | Seunghan Lee,
Kyungsu Kang,
Chong-Min Kyung:
Temperature- and bus traffic- aware data placement in 3D-stacked cache.
VLSI-SoC 2010: 352-357 |
| 4 | | Kyungsu Kang,
Jungsoo Kim,
Sungjoo Yoo,
Chong-Min Kyung:
Temperature-Aware Integrated DVFS and Power Gating for Executing Tasks With Runtime Distribution.
IEEE Trans. on CAD of Integrated Circuits and Systems 29(9): 1381-1394 (2010) |
| 2007 |
|---|
| 3 | | Kyungsu Kang,
Jungsoo Kim,
Heejun Shim,
Chong-Min Kyung:
Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor.
ACM Great Lakes Symposium on VLSI 2007: 594-599 |
| 2 | | Heejun Shim,
Kyungsu Kang,
Chong-Min Kyung:
Search Area Selective Reuse Algorithm in Motion Estimation.
ICME 2007: 1611-1614 |
| 1 | | Jungsoo Kim,
Kyungsu Kang,
Heejun Shim,
Woong Hwangbo,
Chong-Min Kyung:
Fast estimation of software energy consumption using IPI(Inter-Prefetch Interval) energy model.
VLSI-SoC 2007: 224-229 |
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