 | 2011 |
|---|
| 7 |       | Tae-Ho Kim,
Jong-Seok Han,
Sang-Soon Im,
Jae-Young Jang,
Jin-Ku Kang:
A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement.
ESSCIRC 2011: 351-354 |
| 6 | | Tae-Ho Kim,
Yong-Hwan Moon,
Jin-Ku Kang:
A 4 Gb/s Adaptive FFE/DFE Receiver with a Data-Dependent Jitter Measurement.
IEICE Transactions 94-C(11): 1779-1786 (2011) |
| 2010 |
|---|
| 5 | | Sang-Ho Kim,
Hyung-Min Park,
Tae-Ho Kim,
Jin-Ku Kang,
Jin-Ho Kim,
Jae-Youl Lee,
Yoon-Kyung Choi,
Myunghee Lee:
A 1.7Gbps DLL-based Clock Data Recovery in 0.35µm CMOS.
SoCC 2010: 84-87 |
| 4 | | Jae-Wook Yoo,
Tae-Ho Kim,
Dong-Kyun Kim,
Jin-Ku Kang:
A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2.
SoCC 2010: 88-91 |
| 2009 |
|---|
| 3 | | Seungwon Lee,
Tae-Ho Kim,
Jae-Wook Yoo,
Jin-Ku Kang:
A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18μm CMOS.
SoCC 2009: 179-182 |
| 2005 |
|---|
| 2 | | Hyung-Wook Jang,
Sung-Sop Lee,
Jin-Ku Kang:
A clock recovery circuit using half-rate 4×-oversampling PD.
ISCAS (3) 2005: 2192-2195 |
| 2001 |
|---|
| 1 | | Jin-Ku Kang,
Dong-Hee Kim:
A CMOS clock and data recovery with two-XOR phase-frequency detector circuit.
ISCAS (4) 2001: 266-269 |
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