 | 2011 |
|---|
| 11 |       | Byung-Do Yang,
Yong-Kyu Lee,
Si-Woo Sung,
Jae-Joong Min,
Jae-Mun Oh,
Hyeong-Ju Kang:
A Low Power Content Addressable Memory Using Low Swing Search Lines.
IEEE Trans. on Circuits and Systems 58-I(12): 2849-2858 (2011) |
| 10 | | Hyeong-Ju Kang,
Seung Jae Lee,
Byung-Do Yang:
Area-Efficient Prefilter Architecture for a CDMA Receiver.
IEEE Trans. on Circuits and Systems 58-II(4): 220-224 (2011) |
| 2005 |
|---|
| 9 | | Hyeong-Ju Kang,
In-Cheol Park:
SAT-based unbounded symbolic model checking.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 129-140 (2005) |
| 2003 |
|---|
| 8 | | Hyeong-Ju Kang,
In-Cheol Park:
SAT-based unbounded symbolic model checking.
DAC 2003: 840-843 |
| 7 | | Sung-Won Lee,
Hyeong-Ju Kang,
In-Cheol Park:
A 24-bit floating-point audio DSP controller supporting fast exponentiation.
ISCAS (2) 2003: 748-751 |
| 6 | | Hyeong-Ju Kang,
In-Cheol Park:
Pairing and ordering to reduce hardware complexity in cascade form filter design.
ISCAS (4) 2003: 265-268 |
| 2002 |
|---|
| 5 | | Hyeong-Ju Kang,
In-Cheol Park:
A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure.
ICASSP 2002: 3180-3183 |
| 4 | | In-Cheol Park,
Hyeong-Ju Kang:
Digital filter synthesis based on an algorithm to generate all minimal signed digit representations.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1525-1529 (2002) |
| 2001 |
|---|
| 3 | | In-Cheol Park,
Hyeong-Ju Kang:
Digital Filter Synthesis Based on Minimal Signed Digit Representation.
DAC 2001: 468-473 |
| 2 | | Hyeong-Ju Kang,
In-Cheol Park:
Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders.
ISCAS (2) 2001: 693-696 |
| 2000 |
|---|
| 1 |  | Hyeong-Ju Kang,
Hansoo Kim,
In-Cheol Park:
FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders.
ICCAD 2000: 51-54 |
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