 | 2012 |
| 8 |  | Kouichi Kanda,
Yoichi Kawano,
Takao Sasaki,
Noriaki Shirai,
Tetsuro Tamura,
Shigeaki Kawai,
Masahiro Kudo,
Tomotoshi Murakami,
Hiroyuki Nakamoto,
Nobumasa Hasegawa,
Hideki Kano,
Nobuhiro Shimazui,
Akiko Mineyama,
Kazuaki Oishi,
Masashi Shima,
Naoyoshi Tamura,
Toshihide Suzuki,
Toshihiko Mori,
Kimitoshi Niratsuka,
Shinji Yamaura:
A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets.
ISSCC 2012: 86-88 |
| 2011 |
| 7 |  | Keita Takatsu,
Hirotaka Tamura,
Takuji Yamamoto,
Yoshiyasu Doi,
Kouichi Kanda,
Takayuki Shibasaki,
Tadahiro Kuroda:
A 60-GHz Injection-Locked Frequency Divider Using Multi-Order LC Oscillator Topology for Wide Locking Range.
IEICE Transactions 94-C(6): 1049-1052 (2011) |
| 2010 |
| 6 |  | Keita Takatsu,
Hirotaka Tamura,
Takuji Yamamoto,
Yoshiyasu Doi,
Kouichi Kanda,
Takayuki Shibasaki,
Tadahiro Kuroda:
A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS.
CICC 2010: 1-4 |
| 5 |  | Nikola Nedovic,
Anders Kristensson,
Samir Parikh,
Subodh M. Reddy,
Scott McLeod,
Nestoras Tzartzanis,
Kouichi Kanda,
Takuji Yamamoto,
Satoshi Matsubara,
Masaya Kibune,
Yoshiyasu Doi,
Satoshi Ide,
Yukito Tsunoda,
Tetsuji Yamabana,
Takayuki Shibasaki,
Yasumoto Tomita,
Takayuki Hamada,
Mariko Sugawara,
Tadashi Ikeuchi,
Naoki Kuwata,
Hirotaka Tamura,
Junji Ogawa,
William W. Walker:
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.
J. Solid-State Circuits 45(10): 2016-2029 (2010) |
| 2009 |
| 4 |  | Kouichi Kanda,
Hirotaka Tamura,
Takuji Yamamoto,
Satoshi Matsubara,
Masaya Kibune,
Yoshiyasu Doi,
Takayuki Shibasaki,
Nestoras Tzartzanis,
Anders Kristensson,
Samir Parikh,
Satoshi Ide,
Yukito Tsunoda,
Tetsuji Yamabana,
Mariko Sugawara,
Naoki Kuwata,
Tadashi Ikeuchi,
Junji Ogawa,
William W. Walker:
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.
ISSCC 2009: 360-361 |
| 2007 |
| 3 |  | Takayuki Shibasaki,
Hirotaka Tamura,
Kouichi Kanda,
Hisakatsu Yamaguchi,
Junji Ogawa,
Tadahiro Kuroda:
18-GHz Clock Distribution Using a Coupled VCO Array.
IEICE Transactions 90-C(4): 811-822 (2007) |
| 2006 |
| 2 |  | Hirotaka Tamura,
Masaya Kibune,
Hisakatsu Yamaguchi,
Kouichi Kanda,
Kohtaroh Gotoh,
Hideki Ishida,
Junji Ogawa:
Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies.
IEICE Transactions 89-C(3): 300-313 (2006) |
| 2005 |
| 1 |  | Kyeong-Sik Min,
Kouichi Kanda,
Hiroshi Kawaguchi,
Kenichi Inagaki,
Fayez Robert Saliba,
Hoon-Dae Choi,
Hyun-Young Choi,
Daejeong Kim,
Dong Myong Kim,
Takayasu Sakurai:
Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's.
IEICE Transactions 88-C(4): 760-767 (2005) |