 | 2010 |
| 15 |  | Takashi Sato,
Toshiki Kanamoto,
Saiko Kobayashi,
Nobuhiko Goto,
Takao Sato,
Hitoshi Sugihara,
Hiroo Masuda:
A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance.
IEICE Transactions 93-A(9): 1605-1611 (2010) |
| 14 |  | Toshiki Kanamoto,
Takaaki Okumura,
Katsuhiro Furukawa,
Hiroshi Takafuji,
Atsushi Kurokawa,
Koutaro Hachiya,
Tsuyoshi Sakata,
Masakazu Tanaka,
Hidenari Nakashima,
Hiroo Masuda,
Takashi Sato,
Masanori Hashimoto:
Impact of Self-Heating in Wire Interconnection on Timing.
IEICE Transactions 93-C(3): 388-392 (2010) |
| 13 |  | Kenta Yamada,
Toshiyuki Syo,
Hisao Yoshimura,
Masaru Ito,
Tatsuya Kunikiyo,
Toshiki Kanamoto,
Shigetaka Kumashiro:
Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns.
IEICE Transactions 93-C(8): 1349-1358 (2010) |
| 2009 |
| 12 |  | Tsuyoshi Sakata,
Takaaki Okumura,
Atsushi Kurokawa,
Hidenari Nakashima,
Hiroo Masuda,
Takashi Sato,
Masanori Hashimoto,
Koutaro Hachiya,
Katsuhiro Furukawa,
Masakazu Tanaka,
Hiroshi Takafuji,
Toshiki Kanamoto:
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability.
IEICE Transactions 92-A(12): 3016-3023 (2009) |
| 11 |  | Takaaki Okumura,
Atsushi Kurokawa,
Hiroo Masuda,
Toshiki Kanamoto,
Masanori Hashimoto,
Hiroshi Takafuji,
Hidenari Nakashima,
Nobuto Ono,
Tsuyoshi Sakata,
Takashi Sato:
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations.
IEICE Transactions 92-A(4): 990-997 (2009) |
| 2008 |
| 10 |  | Toshiki Kanamoto,
Yasuhiro Ogasahara,
Keiko Natsume,
Kenji Yamaguchi,
Hiroyuki Amishiro,
Tetsuya Watanabe,
Masanori Hashimoto:
Impact of Well Edge Proximity Effect on Timing.
IEICE Transactions 91-A(12): 3461-3464 (2008) |
| 9 |  | Keiichi Suemitsu,
Toshiaki Ito,
Toshiki Kanamoto,
Masayuki Terai,
Satoshi Kotani,
Shigeo Sawada:
A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults.
IEICE Transactions 91-A(12): 3524-3530 (2008) |
| 2007 |
| 8 |  | Masahiko Omura,
Toshiki Kanamoto,
Michiko Tsukamoto,
Mitsutoshi Shirota,
Takashi Nakajima,
Masayuki Terai:
A Fast Characterizing Method for Large Embedded Memory Modules on SoC.
IEICE Transactions 90-A(4): 815-822 (2007) |
| 2006 |
| 7 |  | Toshiki Kanamoto,
Tatsuhiko Ikeda,
Akira Tsuchiya,
Hidetoshi Onodera,
Masanori Hashimoto:
Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design.
IEICE Transactions 89-A(12): 3560-3568 (2006) |
| 6 |  | Toshiki Kanamoto,
Shigekiyo Akutsu,
Tamiyo Nakabayashi,
Takahiro Ichinomiya,
Koutaro Hachiya,
Atsushi Kurokawa,
Hiroshi Ishikawa,
Sakae Muromoto,
Hiroyuki Kobayashi,
Masanori Hashimoto:
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation.
IEICE Transactions 89-A(12): 3666-3670 (2006) |
| 5 |  | Atsushi Kurokawa,
Akira Kasebe,
Toshiki Kanamoto,
Yun Yang,
Zhangcai Huang,
Yasuaki Inoue,
Hiroo Masuda:
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills.
IEICE Transactions 89-A(4): 847-855 (2006) |
| 2005 |
| 4 |  | Atsushi Kurokawa,
Toshiki Kanamoto,
Tetsuya Ibe,
Akira Kasebe,
Wei Fong Chang,
Tetsuro Kage,
Yasuaki Inoue,
Hiroo Masuda:
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills.
ISQED 2005: 586-591 |
| 3 |  | Atsushi Kurokawa,
Toshiki Kanamoto,
Akira Kasebe,
Yasuaki Inoue,
Hiroo Masuda:
A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills.
IEICE Transactions 88-A(11): 3180-3187 (2005) |
| 2 |  | Toshiki Kanamoto,
Tetsuya Watanabe,
Mitsutoshi Shirota,
Masayuki Terai,
Tatsuya Kunikiyo,
Kiyoshi Ishikawa,
Yoshihide Ajioka,
Yasutaka Horiba:
A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures.
IEICE Transactions 88-A(12): 3463-3470 (2005) |
| 1 |  | Atsushi Kurokawa,
Toshiki Kanamoto,
Tetsuya Ibe,
Akira Kasebe,
Wei Fong Chang,
Tetsuro Kage,
Yasuaki Inoue,
Hiroo Masuda:
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills.
IEICE Transactions 88-A(12): 3471-3478 (2005) |