Michitaka Kameyama

	2012
113		Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama: Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors. IEICE Transactions 95-D(2): 354-363 (2012)
	2011
112		Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama: An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. ASP-DAC 2011: 89-90
111		Keyvan Kashkouli Nejad, Xiaohong Jiang, Michitaka Kameyama: High Performance Tag Singulation for Memory-Less RFID Systems. ICC 2011: 1-6
110		Maarti nLukac, Marek A. Perkowski, Michitaka Kameyama: Evolutionary Quantum Logic Synthesis of Boolean Reversible Logic Circuits Embedded in Ternary Quantum Space using Heuristics CoRR abs/1107.3383: (2011)
109		Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama: Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors. IEEE Trans. Circuits Syst. Video Techn. 21(10): 1453-1466 (2011)
108		Shota Ishihara, Masanori Hariyama, Michitaka Kameyama: A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. IEEE Trans. VLSI Syst. 19(8): 1394-1406 (2011)
107		Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions. IEICE Transactions 94-A(1): 342-351 (2011)
106		Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama: Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. IEICE Transactions 94-C(10): 1669-1679 (2011)
105		Kan Watanabe, Masaru Fukushi, Michitaka Kameyama: Adaptive Group-Based Job Scheduling for High Performance and Reliable Volunteer Computing. JIP 19: 39-51 (2011)
	2010
104		Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores. ERSA 2010: 179-186
103		Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, Michitaka Kameyama: An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture. ERSA 2010: 271-274
102		Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama: Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time. ERSA 2010: 281-284
101		Martin Lukac, Michitaka Kameyama, Marek A. Perkowski: Adaptive Selection of Intelligent Processing Modules and its Applications. IC-AI 2010: 513-520
100		Martin Lukac, Marek A. Perkowski, Michitaka Kameyama: Evolutionary quantum logic synthesis of Boolean reversible logic circuits embedded in ternary quantum space using structural restrictions. IEEE Congress on Evolutionary Computation 2010: 1-8
99		Akitaka Ishikawa, Nobuaki Okada, Michitaka Kameyama: Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals. ISMVL 2010: 179-184
98		Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama: Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation. IEICE Transactions 93-A(12): 2570-2580 (2010)
97		Dalia Nashat, Xiaohong Jiang, Michitaka Kameyama: Group Testing Based Detection of Web Service DDoS Attackers. IEICE Transactions 93-B(5): 1113-1121 (2010)
96		Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama: An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. IEICE Transactions 93-C(8): 1338-1348 (2010)
95		Michitaka Kameyama: Foreword. IEICE Transactions 93-D(8): 2025 (2010)
94		Nobuaki Okada, Michitaka Kameyama: Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits. IEICE Transactions 93-D(8): 2126-2133 (2010)
93		Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama: A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals. IEICE Transactions 93-D(8): 2134-2144 (2010)
	2009
92		Shota Ishihara, Masanori Hariyama, Michitaka Kameyama: A low-power FPGA based on autonomous fine-grain power-gating. ASP-DAC 2009: 119-120
91		Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama: An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. ERSA 2009: 145-150
90		Masanori Hariyama, Keita Tanji, Michitaka Kameyama: FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation. ERSA 2009: 263-266
89		Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama: A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. ERSA 2009: 271-274
88		Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. ERSA 2009: 291-294
87		Wim J. C. Melis, Shuhei Chizuwa, Michitaka Kameyama: Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture. ISMVL 2009: 233-238
86		Nobuaki Okada, Michitaka Kameyama: Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals. ISMVL 2009: 54-59
85		Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama: Optimal Periodic Memory Allocation for Image Processing With Multiple Windows. IEEE Trans. VLSI Syst. 17(3): 403-416 (2009)
84		Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture. IEICE Transactions 92-C(4): 539-549 (2009)
	2008
83		Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. ERSA 2008: 201-207
82		Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama: Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ERSA 2008: 309-310
81		Masanori Hariyama, Kensaku Yamashita, Michitaka Kameyama: FPGA implementation of a vehicle detection algorithm using three-dimensional information. IPDPS 2008: 1-5
80		Nobuaki Okada, Michitaka Kameyama: Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells. ISMVL 2008: 180-185
79		Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages. IEICE Transactions 91-A(12): 3596-3606 (2008)
78		Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama: Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling. IEICE Transactions 91-C(4): 479-486 (2008)
77		Hasitha Muthumala Waidyasooriya, Weisheng Chong, Masanori Hariyama, Michitaka Kameyama: Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment. IEICE Transactions 91-C(4): 517-525 (2008)
76		Masanori Hariyama, Shota Ishihara, Michitaka Kameyama: Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture. IEICE Transactions 91-C(9): 1419-1426 (2008)
75		Nobuaki Okada, Michitaka Kameyama: Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation. IEICE Transactions 91-C(9): 1437-1443 (2008)
74		Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama: Memory Allocation for Multi-Resolution Image Processing. IEICE Transactions 91-D(10): 2386-2397 (2008)
	2007
73		Nobuaki Okada, Michitaka Kameyama: Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. ISMVL 2007: 25
72		Tasuku Ito, Michitaka Kameyama: Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. ISMVL 2007: 39
71		Michitaka Kameyama: Special Section on VLSI Technology toward Frontiers of New Market. IEICE Transactions 90-C(10): 1849 (2007)
70		Tasuku Ito, Michitaka Kameyama: Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. Multiple-Valued Logic and Soft Computing 13(4-6): 553-568 (2007)
69		Nobuaki Okada, Michitaka Kameyama: Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. Multiple-Valued Logic and Soft Computing 13(4-6): 619-632 (2007)
	2006
68		W. H. Muthumala, Masanori Hariyama, Michitaka Kameyama: GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design. APCCAS 2006: 1264-1267
67		Masanori Hariyama, Michitaka Kameyama: A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment. APCCAS 2006: 1803-1806
66		Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama: Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal. IPDPS 2006
65		Haque Mohammad Munirul, Michitaka Kameyama: Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit. ISMVL 2006: 13
64		Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama: Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ISMVL 2006: 17
63		Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama: Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture. ISMVL 2006: 6
62		Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi: Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors. ISVLSI 2006: 193-198
61		Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama: Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification. IEICE Transactions 89-C(11): 1551-1558 (2006)
60		Masanori Hariyama, Sho Ogata, Michitaka Kameyama: A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates. IEICE Transactions 89-C(11): 1655-1661 (2006)
	2005
59		Weisheng Chong, Sho Ogata, Masanori Hariyama, Michitaka Kameyama: Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory. IPDPS 2005
58		Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi: VLSI architecture based on packet data transfer scheme and its application. ISCAS (2) 2005: 1786-1789
57		Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama: Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer. ISMVL 2005: 114-119
56		Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama: Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic. ISMVL 2005: 120-125
55		Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama: Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs. ISVLSI 2005: 46-50
54		Masanori Hariyama, Tetsuya Aoyama, Michitaka Kameyama: Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages. IEEE Trans. Computers 54(6): 642-650 (2005)
53		Weisheng Chong, Masanori Hariyama, Michitaka Kameyama: Low-Power Field-Programmable VLSI Using Multiple Supply Voltages. IEICE Transactions 88-A(12): 3298-3305 (2005)
52		Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama: FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture. IEICE Transactions 88-A(12): 3516-3522 (2005)
51		Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama: Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access. IEICE Transactions 88-D(7): 1486-1491 (2005)
	2004
50		Haque Mohammad Munirul, Michitaka Kameyama: Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic. ISMVL 2004: 26-30
49		Haque Mohammad Munirul, Michitaka Kameyama: Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications. ISMVL 2004: 328-333
48		Weisheng Chong, Masanori Hariyama, Michitaka Kameyama: Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. ISVLSI 2004: 243-248
47		Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama: Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure. ISVLSI 2004: 258-259
	2003
46		Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Dynamic Source-Coupled Logic. ISMVL 2003: 207-212
45		Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama: Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic. ISMVL 2003: 99-104
	2002
44		Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama: Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition. ISMVL 2002: 161-
43		Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama: Fully Source-Coupled Logic Based Multiple-Valued VLSI. ISMVL 2002: 270-275
42		Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama: High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph. ISVLSI 2002: 95-100
	2001
41		Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama: VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection. ICRA 2001: 1168-1173
40		Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, C. Zukeran: Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits. ISMVL 2001: 167-172
39		Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama: Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources. ISMVL 2001: 21-26
	2000
38		Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. ISMVL 2000: 382-
37		Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama: DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. ISMVL 2000: 423-429
36		Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama: Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. ISMVL 2000: 438-
35		Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. PRDC 2000: 27-36
34		Masanori Hariyama, Seunghwan Lee, Michitaka Kameyama: Architecture of a high-performance stereo vision VLSI processor. Advanced Robotics 14(5): 329-332 (2000)
	1999
33		Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic. ISMVL 1999: 275-279
32		Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama: Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs. ISMVL 1999: 30-35
31		Yoshichika Fujioka, Michitaka Kameyama: Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture. Systems and Computers in Japan 30(12): 43-51 (1999)
	1998
30		Masanori Hariyama, Michitaka Kameyama: Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products. ICRA 1998: 3691-3696
29		Takahiro Hanyu, Takahiro Saito, Michitaka Kameyama: Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic. ISMVL 1998: 134-139
28		Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama: Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI. ISMVL 1998: 270-275
27		Takahiro Saito, Takahiro Hanyu, Michitaka Kameyama: Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application. Systems and Computers in Japan 29(11): 40-47 (1998)
26		Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama: Design and evaluation of a digit-parallel multiple-valued content-addressable memory. Systems and Computers in Japan 29(11): 48-54 (1998)
	1997
25		Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama: One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing. ISMVL 1997: 175-
24		Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama: A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects. Systems and Computers in Japan 28(2): 54-61 (1997)
	1996
23		Masami Nakajima, Michitaka Kameyama: Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy. ISMVL 1996: 104-109
22		Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama: Quaternary Universal-Literal CAM for Cellular Logic Image Processing. ISMVL 1996: 224-229
21		Shoji Kawahito, Makoto Ishida, Tasuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi: Author's Reply. IEEE Trans. Computers 45(5): 639 (1996)
	1995
20		M. Ryu, Michitaka Kameyama: Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices. ISMVL 1995: 20-
19		Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. ISMVL 1995: 64-
18		Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama: Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. ISMVL 1995: 92-97
17		Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama: Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate. IEICE Transactions 78-D(8): 951-958 (1995)
	1994
16		Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic. ISMVL 1994: 19-26
15		Masami Nakajima, Michitaka Kameyama: Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k-Ary Operations. ISMVL 1994: 223-230
14		Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi: High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. IEEE Trans. Computers 43(1): 34-42 (1994)
	1993
13		Yoshichika Fujioka, Michitaka Kameyama: 2400-MFLOPS Reconfigurable Parallel VLSI Processor for Robot Control. ICRA (3) 1993: 149-154
12		Masami Nakajima, Michitaka Kameyama: Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations. ISMVL 1993: 283-288
	1992
11		Katsuhiko Shimabukuro, Michitaka Kameyama, Tatsuo Higuchi: Design of a Multiple-Valued VLSI Processor for Digital Control. ISMVL 1992: 322-329
10		Makoto Honda, Michitaka Kameyama, Tatsuo Higuchi: Residue Arithmetic Based Multiple-Valued VLSI Image Processor. ISMVL 1992: 330-336
9		Saneaki Tamaki, Michitaka Kameyama, Tatsuo Higuchi: Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits. ISMVL 1992: 382-388
8		Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi: Interconnection-Free Biomolecular Computing. IEEE Computer 25(11): 41-50 (1992)
	1991
7		Somchai Kittichaikoonkit, Michitaka Kameyama, Tatsuo Higuchi: High-Performance VLSI Processor for Robot Inverse Dynamics Computation. ICCD 1991: 608-611
6		Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi: Design of Interconnection-Free Biomolecular Computing System. ISMVL 1991: 173-180
	1990
5		Michitaka Kameyama: Toward the Age of Beyond-Binary Electronics and Systems. ISMVL 1990: 162-166
4		Michitaka Kameyama, Masahiro Nomura, Tatsuo Higuchi: Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System. ISMVL 1990: 355-362
	1988
3		Michitaka Kameyama, Shoji Kawahito, Tatsuo Higuchi: A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits. IEEE Computer 21(4): 43-56 (1988)
	1977
2		Tatsuo Higuchi, Michitaka Kameyama: Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters. IEEE Trans. Computers 26(12): 1212-1221 (1977)
1		Michitaka Kameyama, Tatsuo Higuchi: Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module. IEEE Trans. Computers 26(12): 1297-1302 (1977)

Coauthor Index

1	Takafumi Aoki	[6] [8]
2	Tetsuya Aoyama	[54]
3	Manabu Arakaki	[22] [25]
4	Yuichi Araumi	[24]
5	Shuhei Chizuwa	[87]
6	Weisheng Chong	[48] [53] [55] [59] [77]
7	Xiaowei Deng	[17] [18]
8	Yoshichika Fujioka	[13] [31] [58]
9	Masaru Fukushi	[105]
10	Takahiro Hanyu	[16] [17] [18] [19] [22] [25] [26] [27] [28] [29] [32] [33] [35] [36] [37] [38] [39] [40] [43] [44] [45] [46]
11	Masanori Hariyama	[24] [30] [34] [41] [42] [47] [48] [51] [52] [53] [54] [55] [59] [60] [61] [62] [64] [66] [67] [68] [74] [76] [77] [78] [79] [81] [82] [83] [84] [85] [88] [89] [90] [91] [92] [93] [96] [98] [102] [103] [104] [106] [107] [108] [109] [112] [113]
12	Tomoaki Hasegawa	[56] [57] [63]
13	Tatsuo Higuchi	[1] [2] [3] [4] [6] [7] [8] [9] [10] [11] [14] [21]
14	Yuya Homma	[57] [58]
15	Makoto Honda	[10]
16	Noriaki Idobata	[82] [89] [93]
17	Tsukasa Ike	[33] [35] [38] [39] [43]
18	Makoto Ishida	[14] [21]
19	Shota Ishihara	[76] [82] [89] [91] [92] [93] [96] [103] [106] [108] [112]
20	Akitaka Ishikawa	[99]
21	Tasuku Ito	[70] [72]
22	Xiaohong Jiang	[97] [111]
23	Shunichi Kaeriyama	[36]
24	Shoji Kawahito	[3] [14] [21]
25	Hiromitsu Kimura	[32] [37] [44]
26	Somchai Kittichaikoonkit	[7]
27	Yasuhiro Kobayashi	[52] [62] [74] [85]
28	Yoshiya Komatsu	[91] [96] [106] [112]
29	Seunghwan Lee	[34]
30	Martin Lukac	[100] [101]
31	Wim J. C. Melis	[87]
32	Akira Mochizuki	[16] [19] [46]
33	Haque Mohammad Munirul	[49] [50] [56] [63] [65]
34	W. H. Muthumala	[68]
35	Masami Nakajima	[12] [15] [23]
36	Tasuro Nakamura	[21]
37	Tetsuro Nakamura	[14]
38	Yoshihiro Nakatani	[64] [66]
39	Dalia Nashat	[97]
40	Keyvan Kashkouli Nejad	[111]
41	Masahiro Nomura	[4]
42	Sho Ogata	[55] [59] [60]
43	Yosuke Ohbayashi	[109] [113]
44	Naotaka Ohsawa	[42] [47]
45	Nobuaki Okada	[69] [73] [75] [80] [86] [94] [99]
46	Daisuke Okumura	[98] [102]
47	Marek A. Perkowski	[100] [101] [110]
48	M. Ryu	[20]
49	Takahiro Saito	[27] [29]
50	Osamu Sakamoto	[47]
51	Haruka Sasaki	[51] [52]
52	Katsuhiko Shimabukuro	[11] [40]
53	Tomohiro Takahashi	[45]
54	Toshiki Takeuchi	[41]
55	Saneaki Tamaki	[9]
56	Keita Tanji	[90]
57	Kaname Teranishi	[26] [28]
58	Nobuhiro Tomabechi	[58]
59	Ryoto Tsuchiya	[103] [106]
60	Hasitha Muthumala Waidyasooriya	[77] [79] [83] [84] [88] [98] [102] [104] [107] [109] [113]
61	Kan Watanabe	[105]
62	Shigeo Yamadera	[61]
63	Kensaku Yamashita	[81]
64	Naoto Yokoyama	[78]
65	C. Zukeran	[40]
66	Maarti nLukac	[110]

Colors in the list of coauthors

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