Yoji Kajitani

	2008
50		Yoji Kajitani: Floorplan and Placement. Encyclopedia of Algorithms 2008
	2007
49		Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani: A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os. IEICE Transactions 90-A(5): 924-931 (2007)
	2006
48		Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani: How does partitioning matter for 3D floorplanning? ACM Great Lakes Symposium on VLSI 2006: 73-78
47		Yoji Kajitani: Theory of placement by numDAG related with single-sequence, SP, BSG, and O-tree. ISCAS 2006
46		Takashi Nojima, Nobuto Ono, Shigetoshi Nakatake, Toru Fujimura, Koji Okazaki, Yoji Kajitani: Adaptive Porting of Analog IPs with Reusable Conservative Properties. ISVLSI 2006: 18-23
45		Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani: The Oct-Touched Tile: A New Architecture for Shape-Based Routing. IEICE Transactions 89-A(2): 448-455 (2006)
	2005
44		Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani: The oct-touched tile: a new architecture for shape-based routing. ACM Great Lakes Symposium on VLSI 2005: 126-129
43		Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani: A new approach based on LFF for optimization of dynamic hardware reconfigurations. ISCAS (2) 2005: 1210-1213
42		Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani: Fixed-outline floorplanning with constraints through instance augmentation. ISCAS (2) 2005: 1883-1886
41		Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi: Equidistance routing in high-speed VLSI layout design. Integration 38(3): 439-449 (2005)
	2004
40		Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani: A device-level placement with multi-directional convex clustering. ACM Great Lakes Symposium on VLSI 2004: 196-201
39		Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi: Equidistance routing in high-speed VLSI layout design. ACM Great Lakes Symposium on VLSI 2004: 220-223
38		Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani: Abstraction and optimization of consistent floorplanning with pillar block constraints. ASP-DAC 2004: 19-24
37		Xuliang Zhang, Yoji Kajitani: Space-planning: placement of modules with controlled empty area by single-sequence. ASP-DAC 2004: 25-30
36		Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani: Multi-level placement with circuit schema based clustering in analog IC layouts. ASP-DAC 2004: 406-411
35		Xuliang Zhang, Yoji Kajitani: Theory of T-junction floorplans in terms of single-sequence. ISCAS (5) 2004: 341-344
	2002
34		Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita: Chip size estimation based on wiring area. APCCAS (2) 2002: 113-118
33		Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin: An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees. DATE 2002: 61-68
32		Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita: Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. VLSI Design 2002: 467-472
31		Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani: Consistent floorplanning with hierarchical superconstraints. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 42-49 (2002)
	2001
30		Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani: Consistent floorplanning with super hierarchical constraints. ISPD 2001: 144-149
	2000
29		Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani: Self-reforming routing for stochastic search in VLSI interconnection layout. ASP-DAC 2000: 87-92
28		Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake: Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. VLSI Design 2000: 11
	1999
27		Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani: Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. ASP-DAC 1999: 125-
	1998
26		Tomonori Izumi, Atsushi Takahashi, Yoji Kajitani: Air-Pressure-Model-Based Fast Algorithms for General Floorplan. ASP-DAC 1998: 563-570
25		Shigetoshi Nakatake, Masahiro Furuya, Yoji Kajitani: Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules. ASP-DAC 1998: 571-576
24		Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani: The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. ICCAD 1998: 267-274
23		Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita: The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. ICCAD 1998: 418-425
22		Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani: Module packing based on the BSG-structure and IC layout applications. IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 519-530 (1998)
21		Magnús M. Halldórsson, Shuichi Ueno, Hiroshi Nakao, Yoji Kajitani: Approximating Steiner trees in graphs with restricted weights. Networks 31(4): 283-292 (1998)
	1997
20		Atsushi Takahashi, Kazunori Inoue, Yoji Kajitani: Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. ICCAD 1997: 260-265
19		Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu: Design of minimum and uniform bipartites for optimum connection blocks of FPGA. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1377-1383 (1997)
	1996
18		Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani: Module placement on BSG-structure and IC layout applications. ICCAD 1996: 484-491
17		Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani: VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1518-1524 (1996)
	1995
16		Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani: Rectangle-packing-based module placement. ICCAD 1995: 472-479
15		Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani: Mixed Searching and Proper-Path-Width. Theor. Comput. Sci. 137(2): 253-268 (1995)
	1994
14		Shigetoshi Nakatake, Yoji Kajitani: Channel-driven global routing with consistent placement (extended abstract). ICCAD 1994: 350-355
13		Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu: The Totally-Perfect Bipartite Graph and Its Construction. ISAAC 1994: 541-549
12		Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu: Design of Optimum Totally Perfect Connection-Blocks of FPGA. ISCAS 1994: 221-224
11		Yoji Kajitani, Jun Dong Cho, Majid Sarrafzadeh: New Approximation Results on Graph Matching and related Problems. WG 1994: 343-358
10		Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani: Minimal acyclic forbidden minors for the family of graphs with bounded path-width. Discrete Mathematics 127(1-3): 293-304 (1994)
	1993
9		Wayne Wei-Ming Dai, Yoji Kajitani, Yorihiko Hirata: Optimal single hop multiple bus networks. ISCAS 1993: 2541-2544
8		Tadashi Arai, Shuichi Ueno, Yoji Kajitani: Generalization of aTheorem on the Parametric Maximum Flow Problem. Discrete Applied Mathematics 41(1): 69-74 (1993)
	1991
7		Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani: Mixed-Searching and Proper-Path-Width. ISA 1991: 61-71
	1988
6		Yoji Kajitani, Shuichi Ueno, Hiroshi Miyano: Ordering of the elements of a matroid such that its consecutive w elements are independent. Discrete Mathematics 72(1-3): 187-194 (1988)
5		Shuichi Ueno, Yoji Kajitani, Shin'ya Gotoh: On the nonseparating independent set problem and feedback set problem for graphs with no vertex degree exceeding three. Discrete Mathematics 72(1-3): 355-360 (1988)
	1986
4		Yoji Kajitani, Akio Ishizuka, Shuichi Ueno: Characterization of partial 3-trees in terms of three structures. Graphs and Combinatorics 2(1): 233-246 (1986)
	1984
3		Rachel R. Chen, Yoji Kajitani: The channel expansion problem in layout design. DAC 1984: 388-391
	1983
2		Yoji Kajitani: Order of Channels for Safe Routing and Optimal Compaction of Routing Area. IEEE Trans. on CAD of Integrated Circuits and Systems 2(4): 293-300 (1983)
	1979
1		Tatsuya Kawamoto, Yoji Kajitani: The minimum width routing of A 2-row 2-layer polycell-layout. DAC 1979: 290-296

Coauthor Index

1	Tadashi Arai	[8]
2	Kengo R. Azegami	[28]
3	Rachel R. Chen	[3]
4	Jun Dong Cho	[11]
5	Wayne Wei-Ming Dai	[9]
6	Qing Dong	[48]
7	Sheqin Dong	[42] [43]
8	Ning Fu	[38] [44] [45]
9	Toru Fujimura	[46]
10	Kunihiro Fujiyoshi	[12] [13] [16] [17] [18] [19] [22]
11	Masahiro Furuya	[25]
12	Shin'ya Gotoh	[5]
13	Magnús M. Halldórsson	[21]
14	Yorihiko Hirata	[9]
15	Xianlong Hong	[42] [43]
16	Masato Inagi	[49]
17	Kazunori Inoue	[20]
18	Akio Ishizuka	[4]
19	Tomonori Izumi	[26]
20	Liyan Jin	[33]
21	Masahiro Kawakita	[23] [32] [34]
22	Tatsuya Kawamoto	[1]
23	Yukiko Kubo	[29] [30] [31] [32] [34] [39] [41]
24	Rong Liu	[42]
25	Hiroshi Miyano	[6]
26	Hiroshi Miyashita	[39] [41]
27	Hiroshi Murata	[16] [17] [18] [22]
28	Yuichi Nakamura (Yuhichi Nakamura)	[49]
29	Hiroshi Nakao	[21]
30	Shigetoshi Nakatake	[14] [16] [17] [18] [22] [23] [24] [25] [28] [29] [30] [31] [32] [34] [36] [38] [40] [44] [45] [46]
31	Hiroshi Niitsu	[12] [13] [19]
32	Takashi Nojima	[36] [40] [46]
33	Koji Okazaki	[46]
34	Nobuto Ono	[46]
35	Keishi Sakanushi	[23] [24] [33]
36	Majid Sarrafzadeh	[11]
37	Atsushi Takahashi	[7] [10] [15] [20] [26] [27] [28]
38	Yasuhiro Takashima	[29] [36] [38] [40] [44] [45] [48] [49]
39	Kazuyuki Tateishi	[39] [41]
40	Shuichi Ueno	[4] [5] [6] [7] [8] [10] [15] [21]
41	Yuliang Wu	[43]
42	Tan Yan	[48]
43	Tomoyuki Yoda	[27]
44	Xuliang Zhang	[35] [37]
45	Zhe Zhou	[43]
46	Xiaoke Zhu	[36]
47	Changwen Zhuang	[33]

Colors in the list of coauthors

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