Daher Kaiss

	2009
8		Zurab Khasidashvili, Daher Kaiss, Doron Bustan: A compositional theory for post-reboot observational equivalence checking of hardware. FMCAD 2009: 136-143
	2007
7		Daher Kaiss, Marcelo Skaba, Ziyad Hanna, Zurab Khasidashvili: Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification. FMCAD 2007: 20-26
	2006
6		Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna: Post-reboot Equivalence and Compositional Verification of Hardware. FMCAD 2006: 11-18
5		Daher Kaiss, Silvian Goldenberg, Zurab Khasidashvili: Seqver : A Sequential Equivalence Verifier for Hardware Designs . ICCD 2006
4		Nachum Dershowitz, Jieh Hsiang, Guan-Shieng Huang, Daher Kaiss: Boolean Rings for Intersection-Based Satisfiability. LPAR 2006: 482-496
	2004
3		Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna: Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints. ICCAD 2004: 58-65
2		Nachum Dershowitz, Jieh Hsiang, Guan-Shieng Huang, Daher Kaiss: Boolean Ring Satisfiability. SAT 2004
	2001
1		John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss: CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. CAV 2001: 131-143

Coauthor Index

1	Doron Bustan	[8]
2	Nachum Dershowitz	[2] [4]
3	Silvian Goldenberg	[5]
4	Ziyad Hanna	[1] [3] [6] [7]
5	Jieh Hsiang	[2] [4]
6	Guan-Shieng Huang	[2] [4]
7	Zurab Khasidashvili	[3] [5] [6] [7] [8]
8	John Moondanos	[1]
9	Carl-Johan H. Seger	[1]
10	Marcelo Skaba	[3] [6] [7]

Last update Sat Jun 2 20:57:36 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page