![]() | ![]() |
| 2011 | ||
|---|---|---|
| 4 | Koji Kai, Minoru Fujishima: Prospective Silicon Applications and Technologies in 2025. IEICE Transactions 94-C(4): 386-393 (2011) | |
| 2000 | ||
| 3 | Koji Inoue, Koji Kai, Kazuaki Murakami: Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems. Intelligent Memory Systems 2000: 169-178 | |
| 1999 | ||
| 2 | Koji Inoue, Koji Kai, Kazuaki Murakami: Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. HPCA 1999: 218-222 | |
| 1998 | ||
| 1 | Taku Ohsawa, Koji Kai, Kazuaki Murakami: Optimizing the DRAM refresh count for merged DRAM/logic LSIs. ISLPED 1998: 82-87 | |
| 1 | Minoru Fujishima | [4] |
| 2 | Koji Inoue | [2] [3] |
| 3 | Kazuaki Murakami | [1] [2] [3] |
| 4 | Taku Ohsawa | [1] |
Colors in the list of coauthors
Last update Sat Jun 2 20:57:36 2012 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page