Tetsuro Kage

	2005
5		Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture. ISQED 2005: 153-158
4		Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills. ISQED 2005: 586-591
3		Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills. IEICE Transactions 88-A(12): 3471-3478 (2005)
	2004
2		Chieki Mizuta, Jiro Iwai, Ken Machida, Tetsuro Kage, Hiroo Masuda: Large-scale linear circuit simulation with an inversed inductance matrix. ASP-DAC 2004: 511-516
1		Atsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda: DEPOGIT: dense power-ground interconnect architecture for physical design integrity. ASP-DAC 2004: 517-522

Coauthor Index

1	Wei Fong Chang	[3] [4]
2	Tetsuya Ibe	[3] [4]
3	Yasuaki Inoue	[3] [4] [5]
4	Jiro Iwai	[2]
5	Toshiki Kanamoto	[3] [4]
6	Akira Kasebe	[3] [4]
7	Atsushi Kurokawa	[1] [3] [4] [5]
8	Ken Machida	[2]
9	Hiroo Masuda	[1] [2] [3] [4] [5]
10	Chieki Mizuta	[2]
11	Nobuto Ono	[1] [5]
12	Masaharu Yamamoto	[5]

Last update Fri Jun 1 15:44:53 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page