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| 2012 | ||
|---|---|---|
| 5 | Shunichi Kaeriyama, Shinichi Uchida, Masayuki Furumiya, Mitsuji Okada, Tadashi Maeda, Masayuki Mizuno: A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique. J. Solid-State Circuits 47(2): 435-443 (2012) | |
| 2011 | ||
| 4 | Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno: A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests. IEICE Transactions 94-C(1): 102-109 (2011) | |
| 2009 | ||
| 3 | Yasushi Amamiya, Shunichi Kaeriyama, Hidemi Noguchi, Zin Yamazaki, Tomoyuki Yamase, Ken'ichi Hosoya, Minoru Okamoto, Shiro Tomari, Hiroshi Yamaguchi, Hiroaki Shoda, Hironobu Ikeda, Shinji Tanaka, Tsugio Takahashi, Risato Ohhira, Arihide Noda, Ken'ichiro Hijioka, Akira Tanabe, Sadao Fujita, Nobuhiro Kawahara: A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems. ISSCC 2009: 358-359 | |
| 2006 | ||
| 2 | Naoki Banno, Toshitsugu Sakamoto, Noriyuki Iguchi, Hisao Kawaura, Shunichi Kaeriyama, Masayuki Mizuno, Kozuya Terabe, Tsuyoshi Hasegawa, Masakazu Aono: Solid-Electrolyte Nanometer Switch. IEICE Transactions 89-C(11): 1492-1498 (2006) | |
| 2000 | ||
| 1 | Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama: Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. ISMVL 2000: 438- | |
Colors in the list of coauthors
Last update Fri Jun 1 15:44:53 2012 CET by the DBLP Team —
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