Artur Jutman

	2011
20		Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze: Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. Asian Test Symposium 2011: 532-538
19		Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze: SoC and Board Modeling for Processor-Centric Board Testing. DSD 2011: 575-582
18		Artur Jutman, Sergei Devadze, Igor Aleksejev: Invited paper: System-wide fault management based on IEEE P1687 IJTAG. ReCoSoC 2011: 1-4
	2010
17		Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Parallel X-fault simulation with critical path tracing technique. DATE 2010: 879-884
16		Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. DELTA 2010: 14-19
15		Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. DSD 2010: 658-663
14		Anton Tsertov, Artur Jutman, Sergei Devadze: Testing beyond the SoCs in a lego style. EWDTS 2010: 334-338
13		Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman: Fault collapsing with linear complexity in digital circuits. ISCAS 2010: 653-656
12		Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman: Structural fault collapsing by superposition of BDDs for test generation in digital circuits. ISQED 2010: 250-257
	2009
11		Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman: Structurally synthesized multiple input BDDs for simulation of digital circuits. ICECS 2009: 451-454
10		Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar: Fast extended test access via JTAG and FPGAs. ITC 2009: 1-7
	2008
9		Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Parallel fault backtracing for calculation of fault coverage. ASP-DAC 2008: 667-672
8		Artur Jutman, Anton Tsertov, Raimund Ubar: Calculation of LFSR Seed and Polynomial Pair for BIST Applications. DDECS 2008: 275-278
7		Tomas Bengtsson, Shashi Kumar, Raimund Ubar, Artur Jutman, Zebo Peng: Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols. IET Computers & Digital Techniques 2(6): 445-460 (2008)
	2007
6		Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. European Test Symposium 2007: 131-136
5		Raimund Ubar, Artur Jutman, Margus Kruus, Elmet Orasson, Sergei Devadze, Heinz-Dietrich Wuttke: Learning Digital Test and Diagnostics via Internet. iJOE 3(1): (2007)
	2006
4		Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng: Off-Line Testing of Delay Faults in NoC Interconnects. DSD 2006: 677-680
	2005
3		Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov: An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. DSD 2005: 412-419
2		Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman: Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. EDCC 2005: 332-344
	2001
1		Raimund Ubar, Artur Jutman, Zebo Peng: Timing simulation of digital circuits with binary decision diagrams. DATE 2001: 460-466

Coauthor Index

1	Igor Aleksejev	[10] [18]
2	Tomas Bengtsson	[4] [7]
3	Sergei Devadze	[2] [5] [6] [9] [10] [14] [15] [16] [17] [18] [19] [20]
4	Margus Kruus	[5]
5	Shashi Kumar	[4] [7]
6	Dmitri Mironov	[11] [12] [13] [15]
7	Elmet Orasson	[5]
8	Zebo Peng	[1] [4] [7]
9	Jaan Raik	[2] [3] [6] [9] [11] [12] [13] [15] [16] [17]
10	Anton Tsertov	[8] [14] [19] [20]
11	Raimund Ubar	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [15] [16] [17] [19] [20]
12	V. Vislogubov	[3]
13	Heinz-Dietrich Wuttke	[5]

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