 | 2011 |
|---|
| 8 |       | Won-Young Jung,
Jong-Min Kim,
Jin-Soo Kim,
Taek-Soo Kim:
A Precision Floating-Gate Mismatch Measurement Technique for Analog Application.
IEICE Transactions 94-C(5): 780-785 (2011) |
| 7 | | Jae-Young Park,
Dae-Woo Kim,
Young-Sang Son,
Jong-Kyu Song,
Chang-Soo Jang,
Won-Young Jung:
A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35 µm Bipolar-CMOS-DMOS Process.
IEICE Transactions 94-C(5): 796-801 (2011) |
| 2010 |
|---|
| 6 | | Jae-Young Park,
Jong-Kyu Song,
Dae-Woo Kim,
Chang-Soo Jang,
Won-Young Jung,
Taek-Soo Kim:
On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs.
IEICE Transactions 93-C(5): 625-630 (2010) |
| 2009 |
|---|
| 5 | | Jae-Young Park,
Jong-Kyu Song,
Chang-Soo Jang,
San-Hong Kim,
Won-Young Jung,
Taek-Soo Kim:
A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits.
IEICE Transactions 92-C(5): 671-675 (2009) |
| 2008 |
|---|
| 4 | | Won-Young Jung,
Hyungon Kim,
Yong-Ju Kim,
Jae-Kyung Wee:
Novel Method of Interconnect Worstcase Establishment with Statistically-Based Approaches.
IEICE Transactions 91-A(4): 1177-1184 (2008) |
| 2007 |
|---|
| 3 | | Ji-Hoon Lim,
Jong-Chan Ha,
Won-Young Jung,
Yong-Ju Kim,
Jae-Kyung Wee:
A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips.
IEICE Transactions 90-C(3): 644-648 (2007) |
| 2006 |
|---|
| 2 | | Yong-Ju Kim,
Won-Young Jung,
Jae-Kyung Wee:
Fast and Accurate Power Bus Designer for Multi-Layers High-Speed Digital Boards.
IEICE Transactions 89-C(7): 1097-1105 (2006) |
| 1995 |
|---|
| 1 | | Won-Young Jung,
Ghun-Up Cha,
Young-Bae Kim,
Jun-Ho Baek,
Choon-Kyung Kim:
Integrated interconnect circuit modeling for VLSI design.
ASP-DAC 1995 |
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