 | 2012 |
|---|
| 8 |       | Minje Jun,
Deumji Woo,
Eui-Young Chung:
Partial Connection-Aware Topology Synthesis for On-Chip Cascaded Crossbar Network.
IEEE Trans. Computers 61(1): 73-86 (2012) |
| 2010 |
|---|
| 7 | | Minje Jun,
Sungroh Yoon,
Eui-Young Chung:
Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network.
DATE 2010: 1390-1395 |
| 6 | | Minje Jun,
Eui-Young Chung:
Design of On-Chip Crossbar Network Topology Using Chained Edge Partitioning.
Comput. J. 53(7): 904-917 (2010) |
| 2009 |
|---|
| 5 | | Minje Jun,
Sungjoo Yoo,
Eui-Young Chung:
Topology Synthesis of Cascaded Crossbar Switches.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(6): 926-930 (2009) |
| 4 | | Jong-Ho Roh,
Minje Jun,
Kwanhu Bang,
Eui-Young Chung:
Jitter-Conscious Bus Arbitration Scheme for Real-Time Systems.
IEICE Transactions 92-A(2): 643-647 (2009) |
| 2008 |
|---|
| 3 | | Minje Jun,
Sungjoo Yoo,
Eui-Young Chung:
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches.
ASP-DAC 2008: 583-588 |
| 2007 |
|---|
| 2 | | Minje Jun,
Kwanhu Bang,
Hyuk-Jun Lee,
Naehyuck Chang,
Eui-Young Chung:
Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems.
ASP-DAC 2007: 159-164 |
| 1 | | Minje Jun,
Kwanhu Bang,
Hyuk-Jun Lee,
Eui-Young Chung:
Latency-Aware Bus Arbitration for Real-Time Embedded Systems.
IEICE Transactions 90-D(3): 676-679 (2007) |
Data released under the ODC-BY 1.0 license — See also our legal information page