Donald A. Joy

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1993

2 Donald A. Joy, Maciej J. Ciesielski: Clock period minimization with wave pipelining. IEEE Trans. on CAD of Integrated Circuits and Systems 12(4): 461-472 (1993)

1991

1 Donald A. Joy, Maciej J. Ciesielski: Placement for Clock Period Minimization With Multiple Wave Propagation. DAC 1991: 640-643

	1993
2		Donald A. Joy, Maciej J. Ciesielski: Clock period minimization with wave pipelining. IEEE Trans. on CAD of Integrated Circuits and Systems 12(4): 461-472 (1993)
	1991
1		Donald A. Joy, Maciej J. Ciesielski: Placement for Clock Period Minimization With Multiple Wave Propagation. DAC 1991: 640-643

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