 | 2002 |
| 12 |  | Robert Cooksey,
Stéphan Jourdan,
Dirk Grunwald:
A stateless, content-directed data prefetching mechanism.
ASPLOS 2002: 279-290 |
| 2001 |
| 11 |  | Pierre Michaud,
André Seznec,
Stéphan Jourdan:
An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors.
International Journal of Parallel Programming 29(1): 35-58 (2001) |
| 2000 |
| 10 |  | Stéphan Jourdan,
Lihu Rappoport,
Yoav Almog,
Mattan Erez,
Adi Yoaz,
Ronny Ronen:
eXtended Block Cache.
HPCA 2000: 61-70 |
| 9 |  | Michael Bekerman,
Adi Yoaz,
Freddy Gabbay,
Stéphan Jourdan,
Maxim Kalaev,
Ronny Ronen:
Early load address resolution via register tracking.
ISCA 2000: 306-315 |
| 1999 |
| 8 |  | Pierre Michaud,
André Seznec,
Stéphan Jourdan:
Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors.
IEEE PACT 1999: 2-10 |
| 7 |  | Adi Yoaz,
Mattan Erez,
Ronny Ronen,
Stéphan Jourdan:
Speculation Techniques for Improving Load Related Instruction Scheduling.
ISCA 1999: 42-53 |
| 6 |  | Michael Bekerman,
Stéphan Jourdan,
Ronny Ronen,
Gilad Kirshenboim,
Lihu Rappoport,
Adi Yoaz,
Uri C. Weiser:
Correlated Load-Address Predictors.
ISCA 1999: 54-63 |
| 1998 |
| 5 |  | Stéphan Jourdan,
Ronny Ronen,
Michael Bekerman,
Bishara Shomar,
Adi Yoaz:
A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification.
MICRO 1998: 216-225 |
| 1997 |
| 4 |  | Stéphan Jourdan,
Jared Stark,
Tse-Hao Hsing,
Yale N. Patt:
Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution.
International Journal of Parallel Programming 25(5): 363-383 (1997) |
| 1996 |
| 3 |  | André Seznec,
Stéphan Jourdan,
Pascal Sainrat,
Pierre Michaud:
Multiple-Block Ahead Branch Predictors.
ASPLOS 1996: 116-127 |
| 1995 |
| 2 |  | Stéphan Jourdan,
Pascal Sainrat,
Daniel Litaize:
Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor.
ISCA 1995: 117-125 |
| 1 |  | Stéphan Jourdan,
Pascal Sainrat,
Daniel Litaize:
An investigation of the performance of various instruction-issue buffer topologies.
MICRO 1995: 279-284 |