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| 2012 | ||
|---|---|---|
| 37 | Cheng-Wen Wei, Sheng-Jie Su, Tian-Sheuan Chang, Shyh-Jye Jou: Sub $\mu$ W Noise Reduction for CIC Hearing Aids. IEEE Trans. VLSI Syst. 20(5): 937-947 (2012) | |
| 2011 | ||
| 36 | Fan-Chiang Yi, Ching-Wen Huang, Tai-Shih Chi, Shyh-Jye Jou: Low power InfomaxICA with compensation strategy for binaural hearing-aid. ISCAS 2011: 2083-2086 | |
| 35 | Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang: 8T single-ended sub-threshold SRAM with cross-point data-aware write operation. ISLPED 2011: 169-174 | |
| 34 | Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu: A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. SoCC 2011: 197-200 | |
| 33 | Li-Rong Wang, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee: Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design. IEICE Transactions 94-C(6): 1112-1119 (2011) | |
| 2010 | ||
| 32 | Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang: Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist. IEEE Trans. on Circuits and Systems 57-I(12): 3039-3047 (2010) | |
| 31 | Hsiao-Yun Chen, Meng-Lin Ku, Shyh-Jye Jou, Chia-Chi Huang: A Robust Channel Estimator for High-Mobility STBC-OFDM Systems. IEEE Trans. on Circuits and Systems 57-I(4): 925-936 (2010) | |
| 2009 | ||
| 30 | Shao-Wei Yen, Ming-Chih Hu, Chin-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee: A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application. CICC 2009: 191-194 | |
| 29 | Yu-Chun Lin, Muh-Tian Shiue, Shyh-Jye Jou: 10Gbps Decision Feedback Equalizer with Dynamic Lookahead Decision Loop. ISCAS 2009: 1839-1842 | |
| 28 | Jihi-Yu Lin, Ming-Hsien Tu, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang: Asymmetrical Write-assist for single-ended SRAM operation. SoCC 2009: 101-104 | |
| 27 | Chih-Hao Liu, Chien-Ching Lin, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou: Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network. IEEE Trans. on Circuits and Systems 56-II(9): 734-738 (2009) | |
| 2008 | ||
| 26 | Jyun-Nan Lin, Hsiao-Yun Chen, Ting-Chen Wei, Shyh-Jye Jou: Symbol and carrier frequency offset synchronization for IEEE802.16e. ISCAS 2008: 3082-3085 | |
| 25 | Li-Rong Wang, Yi-Wei Chiu, Chia-Lin Hu, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee: A reconfigurable MAC architecture implemented with mixed-Vt standard cell library. ISCAS 2008: 3426-3429 | |
| 2007 | ||
| 24 | Wei-Chang Liu, Ting-Chen Wei, Shyh-Jye Jou: Blind Mode/GI Detection and Coarse Symbol Synchronization for DVB-T/H. ISCAS 2007: 2092-2095 | |
| 23 | Jiun-Yi Lin, Li-Rong Wang, Chia-Lin Hu, Shyh-Jye Jou: Mixed-VTH (MVT) CMOS circuit design for low power cell libraries. SoCC 2007: 181-184 | |
| 2006 | ||
| 22 | Ting-Zhen Wei, Shyh-Jye Jou, Muh-Tian Shiue: Memory reduction ICFO estimation architecture for DVB-T. ISCAS 2006 | |
| 2005 | ||
| 21 | Shyh-Jye Jou, Chih-Hsien Lin, Yen-I Wang: A 12.5 Gbps CMOS input sampler for serial link receiver front end. ISCAS (2) 2005: 1055-1058 | |
| 20 | Chih-Hsien Lin, Chang-Hsiao Tsai, Chih-Ning Chen, Shyh-Jye Jou: Multi-Gigabit Pre-Emphasis Design and Analysis for Serial Link. IEICE Transactions 88-C(10): 2009-2019 (2005) | |
| 2004 | ||
| 19 | Chih-Hsien Lin, Chang-Hsiao Tsai, Chih-Ning Chen, Shyh-Jye Jou: 4/2 PAM serial link transmitter with tunable pre-emphasis. ISCAS (1) 2004: 952-958 | |
| 18 | Kai-Yuan Jheng, Shyh-Jye Jou, An-Yeu Wu: A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code. ISCAS (5) 2004: 293-296 | |
| 2003 | ||
| 17 | Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-Jye Jou: Parameterized and low power DSP core for embedded systems. ISCAS (5) 2003: 265-268 | |
| 16 | Ya-Lan Tsao, Wei-Hao Chen, Ming Hsuan Tan, Maw-Ching Lin, Shyh-Jye Jou: Low-Power Embedded DSP Core for Communication Systems. EURASIP J. Adv. Sig. Proc. 2003(13): 1355-1370 (2003) | |
| 2002 | ||
| 15 | Meng-Hung Tsai, Yi-Ting Chen, Wen-Sheng Cheng, Jun-Xian Teng, Shyh-Jye Jou: Sub-word and reduced-width Booth multipliers for DSP applications. ISCAS (3) 2002: 575-578 | |
| 14 | Shyh-Jye Jou, Hsiao Ping Lee, Yi-Ting Chen, Ming Hsuan Tan, Ya-Lan Tsao: An embedded DSP core for wireless communication. ISCAS (4) 2002: 524-527 | |
| 2001 | ||
| 13 | Maw-Ching Lin, Chien-Lung Chen, Ding-Yu Shin, Chin-Hung Lin, Shyh-Jye Jou: Low-power multiplierless FIR filter synthesizer based on CSD code. ISCAS (4) 2001: 666-669 | |
| 12 | Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, Chu King, Chien-Hsiung Lee, Tim Liu: A serial link transceiver for USB2 high-speed mode. ISCAS (4) 2001: 72-75 | |
| 11 | Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou: Intrinsic response for analog module testing using an analog testability bus. ACM Trans. Design Autom. Electr. Syst. 6(2): 226-243 (2001) | |
| 2000 | ||
| 10 | Shyh-Jye Jou, Hui-Hsuan Wang: Fixed-Width Multiplier for DSP Application. ICCD 2000: 318-322 | |
| 1999 | ||
| 9 | Chauchin Su, Shyh-Jye Jou: Decentralized BIST Methodology for System Level Interconnects. J. Electronic Testing 15(3): 255-265 (1999) | |
| 1997 | ||
| 8 | Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou: Parasitic Effect Removal for Analog Measurement in P1149.4 Environment. ITC 1997: 499-508 | |
| 1996 | ||
| 7 | Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting: Syndrome Simulation And Syndrome Test For Unscanned Interconnects. Asian Test Symposium 1996: 62-67 | |
| 6 | Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting: Metrology for analog module testing using analog testability bus. ICCAD 1996: 594-599 | |
| 1995 | ||
| 5 | Chauchin Su, Shenshung Chiang, Shyh-Jye Jou: Impulse response fault model and fault extraction for functional level analog circuit diagnosis. ICCAD 1995: 631-636 | |
| 4 | Shyh-Jye Jou, Kou-Fong Liu, Chauchin Su: Circuits Design Optimization Using Symbolic Approach. ISCAS 1995: 1396-1399 | |
| 3 | Wen-Hsing Hsieh, Shyh-Jye Jou, Chauchin Su: A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors. ISCAS 1995: 574-577 | |
| 1994 | ||
| 2 | Shyh-Jye Jou, Mei-Fang Perng, Chauchin Su, C. K. Wang: Hierarchical Techniques for Symbolic Analysis of Large Electronic Circuits. ISCAS 1994: 21-24 | |
| 1 | Chauchin Su, Kychin Hwang, Shyh-Jye Jou: An IDDQ Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan Environment. ITC 1994: 670-676 | |
Colors in the list of coauthors
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