Jing-Yang Jou

	2012
87		Hsien-Kai Kuo, Kuan-Ting Chen, Bo-Cheng Charles Lai, Jing-Yang Jou: Thread affinity mapping for irregular data access on shared Cache GPGPU. ASP-DAC 2012: 659-664
86		Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou: Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay. IEICE Transactions 95-A(2): 559-566 (2012)
	2011
85		Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou: Equivalence checking of scheduling with speculative code transformations in high-level synthesis. ASP-DAC 2011: 497-502
84		Meng-Chen Wu, Hung-Ming Chen, Jing-Yang Jou: Mixed non-rectangular block packing for non-Manhattan layout architectures. ISQED 2011: 257-262
83		Kuo-An Chen, Tsung-Wei Chang, Meng-Chen Wu, Mango Chia-Tso Chao, Jing-Yang Jou, Sonair Chen: Design-for-debug layout adjustment for FIB probing and circuit editing. ITC 2011: 1-9
	2010
82		Hsien-Kai Kuo, Bo-Cheng Charles Lai, Jing-Yang Jou: Unleash the parallelism of 3DIC partitioning on GPGPU. SoCC 2010: 127-132
81		Bu-Ching Lin, Yu-Hsiang Wang, Juinn-Dar Huang, Jing-Yang Jou: Expandable MDC-based FFT architecture and its generator for high-performance applications. SoCC 2010: 188-192
80		Che-Hua Shih, Ya-Ching Yang, Chia-Chih Yen, Juinn-Dar Huang, Jing-Yang Jou: FSM-Based Formal Compliance Verification of Interface Protocols. J. Inf. Sci. Eng. 26(5): 1601-1617 (2010)
	2009
79		Meng-Jai Tasi, Mango Chia-Tso Chao, Jing-Yang Jou, Meng-Chen Wu: Multiple-Fault Diagnosis Using Faulty-Region Identification. VTS 2009: 123-128
78		Meng-Chen Wu, Ming-Ching Lu, Hung-Ming Chen, Jing-Yang Jou: Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning. ACM Trans. Design Autom. Electr. Syst. 15(1): (2009)
77		Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou: Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM. IEEE Trans. VLSI Syst. 17(5): 723-727 (2009)
76		Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging. IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 272-284 (2009)
	2008
75		Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou: Verification of Pin-Accurate Port Connections. IEEE Design & Test of Computers 25(5): 478-486 (2008)
	2007
74		Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou: A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. ASP-DAC 2007: 165-170
73		Cheng-Yeh Wang, Chih-Bin Kuo, Jing-Yang Jou: Hybrid Wordlength Optimization Methods of Pipelined FFT Processors. IEEE Trans. Computers 56(8): 1105-1118 (2007)
72		Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: Observability Analysis on HDL Descriptions for Effective Functional Validation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1509-1521 (2007)
71		Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, Jing-Yang Jou: A Tableless Approach for High-Level Power Modeling Using Neural Networks. J. Inf. Sci. Eng. 23(1): 71-90 (2007)
	2006
70		Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou: FSM-based transaction-level functional coverage for interface compliance verification. ASP-DAC 2006: 448-453
69		Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou: A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. ASP-DAC 2006: 600-605
68		Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou: Reliable crosstalk-driven interconnect optimization. ACM Trans. Design Autom. Electr. Syst. 11(1): 88-103 (2006)
67		Chia-Chih Yen, Jing-Yang Jou: An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging. IEEE Trans. Computers 55(11): 1356-1366 (2006)
66		Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou: RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2258-2264 (2006)
	2005
65		Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. ASP-DAC 2005: 323-326
64		Liang-Yu Lin, Cheng-Yeh Wang, Pao-Jui Huang, Chih-Chieh Chou, Jing-Yang Jou: Communication-driven task binding for multiprocessor with latency insensitive network-on-chip. ASP-DAC 2005: 39-44
63		Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. ISCAS (4) 2005: 4134-4137
62		Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou: An efficient heterogeneous tree multiplexer synthesis technique. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1622-1629 (2005)
	2004
61		Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: Layout techniques for on-chip interconnect inductance reduction. ASP-DAC 2004: 269-273
60		Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou: Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming. ASP-DAC 2004: 280-283
59		Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou: On compliance test of on-chip bus for SOC. ASP-DAC 2004: 328-333
58		Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing-Yang Jou: Graph Automorphism-Based Algorithm for Determining Symmetric Inputs. ICCD 2004: 417-419
57		Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: RLC effects on worst-case switching pattern for on-chip buses. ISCAS (2) 2004: 945-948
56		Yi-Wei Lin, Jing-Yang Jou: An efficient approach for hierarchical submodule extraction. ISCAS (5) 2004: 237-240
55		Lily Huang, Tai-Ying Jiang, Jing-Yang Jou, Heng-Liang Huang: An efficient logic extraction algorithm using partitioning and circuit encoding. ISCAS (5) 2004: 249-252
54		Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang: Verification on Port Connections. ITC 2004: 830-836
53		Chia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen: A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation. IEEE Design & Test of Computers 21(2): 111-120 (2004)
52		Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao: Simultaneous floor plan and buffer-block optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 694-703 (2004)
	2003
51		Che-Hua Shih, Jing-Yang Jou: An efficient approach for error diagnosis in HDL design. ISCAS (4) 2003: 732-735
50		Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: SoC design integration by using automatic interconnection rectification. ISCAS (4) 2003: 744-747
49		Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou: A Design-for-Verification Technique for Functional Pattern Reduction. IEEE Design & Test of Computers 20(2): 48-55 (2003)
48		Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: Automatic interconnection rectification for SoC design verification based on the port order fault model. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 104-114 (2003)
	2002
47		Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: Effective Error Diagnosis for RTL Designs in HDLs. Asian Test Symposium 2002: 362-367
46		Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou: A Practical Approach to Cycle Bound Estimation for Property Checking. IWLS 2002: 149-154
45		Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: An automorphic approach to verification pattern generation for SoC design verification using port-order fault model. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1225-1232 (2002)
44		Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: On automatic-verification pattern generation for SoC withport-order fault model. IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 466-479 (2002)
43		Heng-Liang Huang, Jing-Yang Jou: Bootstrap Monte Carlo with Adaptive Stratification for Power Estimation. Journal of Circuits, Systems, and Computers 11(4): 333-350 (2002)
	2001
42		Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou: An efficient design-for-verification technique for HDLs. ASP-DAC 2001: 103-108
41		Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model. Asian Test Symposium 2001: 431-436
40		Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: An AVPG for SOC design verification with port order fault model. ISCAS (5) 2001: 259-262
39		Hen-Ming Lin, Jing-Yang Jou: On tri-state buffer inference in HDL synthesis. ISCAS (5) 2001: 45-48
38		Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen: Grouped input power sensitive transition an input sequence compaction technique for power estimation. ISCAS (5) 2001: 471-474
37		Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou: Automatic Functional Vector Generation Using the Interacting FSM Model. ISQED 2001: 372-377
36		Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang: Unified functional decomposition via encoding for FPGA technology mapping. IEEE Trans. VLSI Syst. 9(2): 251-260 (2001)
35		Yi-Jong Yeh, Sy-Yen Kuo, Jing-Yang Jou: Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 172-176 (2001)
	2000
34		Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou: A new method for constructing IP level power model based on power sensitivity. ASP-DAC 2000: 135-140
33		Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu: Collaboration between Industry and Academia in Test Research. Asian Test Symposium 2000: 17-
32		Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou: Optimal reliable crosstalk-driven interconnect optimization. ISPD 2000: 128-133
31		Chien-Nan Jimmy Liu, Jing-Yang Jou: An Automatic Controller Extractor for HDL Descriptions at the RTL. IEEE Design & Test of Computers 17(3): 72-77 (2000)
30		Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen: ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. IEEE Trans. VLSI Syst. 8(4): 392-400 (2000)
29		Hen-Ming Lin, Jing-Yang Jou: On computing the minimum feedback vertex set of a directed graph bycontraction operations. IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 295-307 (2000)
28		Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou: Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 999-1010 (2000)
	1999
27		Jiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang: Hierarchical Floorplan Design on the Internet. ASP-DAC 1999: 189-192
26		Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang: Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. DAC 1999: 90-95
25		Chien-Nan Jimmy Liu, Jing-Yang Jou: An Efficient Functional Coverage Test for HDL Descriptions at RTL. ICCD 1999: 325-327
24		Hen-Ming Lin, Jing-Yang Jou: Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD. ICCD 1999: 364-
23		Jyh-Mou Tseng, Jing-Yang Jou: Two-level logic minimization for low power. ACM Trans. Design Autom. Electr. Syst. 4(1): 52-69 (1999)
22		Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou: A structure-oriented power modeling technique for macrocells. IEEE Trans. VLSI Syst. 7(3): 380-391 (1999)
	1998
21		Shing-Wu Tung, Jing-Yang Jou: Verification Pattern Generation for Core-Based Design Using Port Order Fault Model. Asian Test Symposium 1998: 402-407
20		Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang: Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. DAC 1998: 712-717
19		Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang: On circuit clustering for area/delay tradeoff under capacity and pin constraints. IEEE Trans. VLSI Syst. 6(4): 634-642 (1998)
18		Shing-Wu Tung, Jing-Yang Jou: A Logical Fault Model for Library Coherence Checking. J. Inf. Sci. Eng. 14(3): 567-586 (1998)
	1997
17		Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou: A power modeling and characterization method for macrocells using structure information. ICCAD 1997: 502-506
16		Jing-Yang Jou, Ming-Chang Nien: Power Driven Partial Scan. ICCD 1997: 642-647
15		Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo: Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 1015-1024 (1997)
	1996
14		Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao: Easily Testable Data Path Allocation Using Input/Output Registers. Asian Test Symposium 1996: 142-
13		Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo: An Efficient PRPG Strategy By Utilizing Essential Faults. Asian Test Symposium 1996: 199-204
12		Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen: An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. ICCAD 1996: 13-17
11		Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou: A power modeling and characterization method for the CMOS standard cell library. ICCAD 1996: 400-404
	1995
10		Jing-Yang Jou: An effective BIST design for PLA. Asian Test Symposium 1995: 286-292
9		Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen: Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. ICCAD 1995: 359-363
8		Jing-Yang Jou, Kwang-Ting (Tim) Cheng: Timing-Driven Partial Scan. IEEE Design & Test of Computers 12(4): 52-59 (1995)
	1992
7		Kwang-Ting Cheng, Jing-Yang Jou: A functional fault model for sequential machines. IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1065-1073 (1992)
	1991
6		Jing-Yang Jou, Kwang-Ting Cheng: Timing-Driven Partial Scan. ICCAD 1991: 404-407
	1990
5		Kwang-Ting Cheng, Jing-Yang Jou: A Single-State-Transition Fault Model for Sequential Machines. ICCAD 1990: 226-229
4		Kwang-Ting Cheng, Jing-Yang Jou: Functional test generation for finite state machines. ITC 1990: 162-168
	1988
3		Ruey-Sing Wei, Steven G. Rothweiler, Jing-Yang Jou: BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping. DAC 1988: 409-414
2		Jing-Yang Jou, Jacob A. Abraham: Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing. ICPP (1) 1988: 359-362
1		Jing-Yang Jou, Jacob A. Abraham: Fault-Tolerant FFT Networks. IEEE Trans. Computers 37(5): 548-561 (1988)

Coauthor Index

1	Jacob A. Abraham	[1] [2]
2	Vishwani D. Agrawal	[33]
3	Tsung-Wei Chang	[83]
4	Yao-Wen Chang	[26] [28] [32] [52] [57] [61] [63] [66] [68]
5	Kai-Yuan Chao	[52]
6	Mango Chia-Tso Chao	[79] [83]
7	Chia-I Chen	[86]
8	Chien-Hua Chen	[69]
9	Hung-Ming Chen	[78] [84]
10	I-Ling Chen	[42] [49]
11	Kuan-Ting Chen	[87]
12	Kuang-Chien Chen	[46] [53]
13	Kuo-An Chen	[83]
14	Sonair Chen	[83]
15	Yeong-Ren Chen	[38]
16	Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng)	[4] [5] [6] [7] [8] [33]
17	Chen-Ling Chou	[58]
18	Chih-Chieh Chou	[64]
19	Hsien-Ho Chuang	[19]
20	Wen-Tsan Hsieh	[71]
21	Chih-Yang Hsu	[71]
22	Wan-Ling Hsu	[86]
23	Heng-Liang Huang	[34] [38] [43] [55]
24	Hsu-Wei Huang	[60] [62]
25	Juinn-Dar Huang	[9] [12] [19] [20] [30] [36] [54] [69] [70] [74] [75] [77] [80] [81] [85] [86]
26	Li-Ren Huang	[13] [14] [15]
27	Lily Huang	[55]
28	Pao-Jui Huang	[64]
29	Iris Hui-Ru Jiang	[26] [27] [28] [32] [52] [68]
30	Jie-Hong Roland Jiang (Jie-Hong R. Jiang)	[20] [36]
31	Tai-Ying Jiang	[47] [55] [65] [72] [76]
32	Chih-Bin Kuo	[73]
33	Hsien-Kai Kuo	[82] [87]
34	Sy-Yen Kuo	[13] [14] [15] [35]
35	Bo-Cheng Lai (Bo-Cheng Charles Lai)	[82] [87]
36	Chi-Hui Lee	[85]
37	Geeng-Wei Lee	[54] [58] [69] [74] [75]
38	Wen-Bin Liao	[14]
39	Bu-Ching Lin	[74] [81]
40	Hen-Ming Lin	[24] [29] [39]
41	Hue-Min Lin	[59]
42	Jiann-Horng Lin	[27]
43	Jiing-Yuan Lin	[11] [17] [22] [34]
44	Liang-Yu Lin	[64]
45	Yen-Ting Lin	[86]
46	Yi-Wei Lin	[56]
47	Chien-Nan Jimmy Liu	[25] [31] [37] [42] [47] [49] [65] [71] [72] [76]
48	Ming-Ching Lu	[78]
49	Ming-Chang Nien	[16]
50	Song-Ra Pan	[32] [68]
51	Steven G. Rothweiler	[3]
52	Wen-Zen Shen	[9] [11] [12] [17] [19] [22] [30] [34] [38]
53	Che-Hua Shih	[51] [59] [70] [77] [80] [85]
54	Man-Yun Su	[70]
55	Meng-Jai Tasi	[79]
56	Jyh-Mou Tseng	[23]
57	Shang-Wei Tu	[57] [61] [63] [66]
58	Shing-Wu Tung	[18] [21] [40] [41] [44] [45] [48] [50]
59	Cheng-Yeh Wang	[60] [62] [64] [73]
60	Chun-Yao Wang	[40] [41] [44] [45] [48] [50] [54] [58] [75]
61	Li-C. Wang	[33]
62	Yu-Hsiang Wang	[81]
63	Ruey-Sing Wei	[3]
64	Chi-Feng Wu	[33]
65	Meng-Chen Wu	[78] [79] [83] [84]
66	Shianling Wu	[33]
67	Ya-Ching Yang	[80]
68	Yi-Jong Yeh	[35]
69	Chia-Chih Yen	[37] [46] [53] [59] [67] [80]

Colors in the list of coauthors

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