 | 2011 |
| 23 |  | Jer-Min Jou,
Yun-Lung Lee,
Sih-Sian Wu:
Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 30(8): 1184-1196 (2011) |
| 2010 |
| 22 |  | Jer-Min Jou,
Sih-Sian Wu,
Yun-Lung Lee,
Cheng Chou,
Yuan-Long Jeang:
New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model.
DAC 2010: 258-261 |
| 21 |  | Jer-Min Jou,
Yun-Lung Lee:
An Optimal Round-Robin Arbiter Design for NoC.
J. Inf. Sci. Eng. 26(6): 2047-2058 (2010) |
| 2009 |
| 20 |  | Yun-Lung Lee,
Jer-Min Jou,
Yen-Yu Chen:
A high-speed and decentralized arbiter design for NoC.
AICCSA 2009: 350-353 |
| 2007 |
| 19 |  | Jer-Min Jou,
Yun-Lung Lee,
Chen-Yen Lin,
Chien-Ming Sun:
A Novel Reconfigurable Computation Unit for DSP Applications.
ISVLSI 2007: 439-444 |
| 2005 |
| 18 |  | Yuan-Long Jeang,
Jer-Min Jou,
Win-Hsien Huang:
A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC).
IEICE Transactions 88-A(12): 3531-3538 (2005) |
| 2004 |
| 17 |  | Yeu-Horng Shiau,
Jer-Min Jou,
Chin-Chi Liu:
Efficient Architectures for the Biorthogonal Wavelet Transform by Filter Bank and Lifting Scheme.
IEICE Transactions 87-D(7): 1867-1877 (2004) |
| 2002 |
| 16 |  | Jer-Min Jou,
Shiann-Rong Kuang,
Yeu-Horng Shiau,
Ren-Der Chen:
Design of a dynamic pipelined architecture for fuzzy color correction.
IEEE Trans. VLSI Syst. 10(6): 924-929 (2002) |
| 2001 |
| 15 |  | Jer-Min Jou,
Yeu-Horng Shiau,
Chin-Chi Liu:
Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme.
ISCAS (2) 2001: 529-532 |
| 14 |  | Pei-Yin Chen,
Jer-Min Jou:
An efficient blocking-matching algorithm based on fuzzy reasoning.
IEEE Transactions on Systems, Man, and Cybernetics, Part B 31(2): 253-259 (2001) |
| 2000 |
| 13 |  | Jer-Min Jou,
Pei-Yin Chen,
Sheng-Fu Yang:
An adaptive fuzzy logic controller: its VLSI architecture and applications.
IEEE Trans. VLSI Syst. 8(1): 52-60 (2000) |
| 1999 |
| 12 |  | Ren-Der Chen,
Jer-Min Jou,
Yeu-Horng Shiau:
Hazard-Free Synthesis and Decomposition of Asynchronous Circuits.
ASP-DAC 1999: 185-188 |
| 11 |  | Jer-Min Jou,
Pei-Yin Chen,
Yeu-Horng Shiau,
Ming-Shiang Liang:
A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform.
ASP-DAC 1999: 205-208 |
| 10 |  | Jer-Min Jou,
Shiann-Rong Kuang,
Yeu-Horng Shiau:
A New Pipelined Architecture for Fuzzy Color Correction.
ASP-DAC 1999: 209- |
| 9 |  | Jer-Min Jou,
Pei-Yin Chen,
Jian-Ming Sun:
The gray prediction search algorithm for block motion estimation.
IEEE Trans. Circuits Syst. Video Techn. 9(6): 843-848 (1999) |
| 8 |  | Jer-Min Jou,
Pei-Yin Chen:
A fast and efficient lossless data-compression method.
IEEE Transactions on Communications 47(9): 1278-1283 (1999) |
| 1997 |
| 7 |  | Shung-Chih Chen,
Jer-Min Jou:
Diagnostic fault simulation for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 299-308 (1997) |
| 6 |  | Shung-Chih Chen,
Jer-Min Jou:
Serial diagnostic fault simulation for synchronous sequential circuits.
Integration 23(2): 157-170 (1997) |
| 1995 |
| 5 |  | Jer-Min Jou,
Shung-Chih Chen:
Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault Partitioning.
ISCAS 1995: 2004-2007 |
| 1994 |
| 4 |  | Jer-Min Jou,
Shung-Chih Chen:
A fast and memory-efficient diagnostic fault simulation for sequential circuits.
ICCAD 1994: 723-726 |
| 3 |  | Jer-Min Jou,
Ren-Der Chen,
Shiann-Rong Kuang:
Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization.
ISCAS 1994: 45-48 |
| 2 |  | Jer-Min Jou,
Shung-Chih Chen,
Ren-Der Chen:
A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits.
ISCAS 1994: 85-88 |
| 1993 |
| 1 |  | Jer-Min Jou,
Shiann-Rong Kuang:
Library-Adaptively Integrated Data Path Synthesis for DSP Systems.
ICCD 1993: 379-382 |