Wen-Ben Jone

	2011
95		Jason Nemeth, Rui Min, Wen-Ben Jone, Yiming Hu: Location Cache Design and Performance Analysis for Chip Multiprocessors. IEEE Trans. VLSI Syst. 19(1): 104-117 (2011)
94		Hao Xu, Ranga Vemuri, Wen-Ben Jone: Dynamic Characteristics of Power Gating During Mode Transition. IEEE Trans. VLSI Syst. 19(2): 237-249 (2011)
93		Hao Xu, Wen-Ben Jone, Ranga Vemuri: Aggressive Runtime Leakage Control Through Adaptive Light-Weight Vth Hopping With Temperature and Process Variation. IEEE Trans. VLSI Syst. 19(7): 1319-1323 (2011)
92		Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu: Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 455-463 (2011)
	2010
91		Hao Xu, Wen-Ben Jone, Ranga Vemuri: Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping. ICCAD 2010: 632-636
90		Hao Xu, Ranga Vemuri, Wen-Ben Jone: Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs. ICCAD 2010: 637-641
89		Hao Xu, Wen-Ben Jone, Ranga Vemuri: Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control. VLSI Design 2010: 51-56
88		Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Hiroshi Furukawa, Hao-Jan Chao, Boryau Sheu, Jianghao Guo, Wen-Ben Jone: Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 299-312 (2010)
87		Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang: Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer. J. Electronic Testing 26(3): 367-392 (2010)
86		Hao Xu, Wen-Ben Jone, Ranga Vemuri: Tuning Vth Hopping for Aggressive Runtime Leakage Control. J. Low Power Electronics 6(3): 447-456 (2010)
	2009
85		Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang, Shianling Wu: Analysis of Resistive Bridging Defects in a Synchronizer. Asian Test Symposium 2009: 443-449
84		Hao Xu, Ranga Vemuri, Wen-Ben Jone: Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage. DATE 2009: 594-597
83		Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang: Analysis of Resistive Open Defects in a Synchronizer. DFT 2009: 164-172
82		Hao Xu, Ranga Vemuri, Wen-Ben Jone: Temporal and spatial idleness exploitation for optimal-grained leakage control. ICCAD 2009: 468-473
81		Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li: Turbo1500: Core-Based Design for Test and Diagnosis. IEEE Design & Test of Computers 26(1): 26-35 (2009)
	2008
80		Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone: Material Fatigue and Reliability of MEMS Accelerometers. DFT 2008: 314-322
79		Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone: Control Circuitry for Self-Repairable MEMS Accelerometers. EIAT/IETA 2008: 265-270
78		Hao Xu, Wen-Ben Jone, Ranga Vemuri: Accurate energy breakeven time estimation for run-time power gating. ICCAD 2008: 161-168
77		Hao Xu, Ranga Vemuri, Wen-Ben Jone: Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW. ICCD 2008: 618-625
76		Hao Xu, Ranga Vemuri, Wen-Ben Jone: Dynamic virtual ground voltage estimation for power gating. ISLPED 2008: 27-32
75		Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li: Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. ITC 2008: 1-9
74		Sunil R. Das, Altaf Hossain, Satyendra Biswas, Emil M. Petriu, Mansour H. Assaf, Wen-Ben Jone, Mehmet Sahinoglu: On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing. IEEE T. Instrumentation and Measurement 57(10): 2146-2168 (2008)
	2007
73		Jianxun Liu, Wen-Ben Jone: An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects. ICCD 2007: 360-367
72		Sunil R. Das, Jila Zakizadeh, Satyendra Biswas, Mansour H. Assaf, Amiya Nayak, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu: Testing Analog and Mixed-Signal Circuits With Built-In Hardware - A New Approach. IEEE T. Instrumentation and Measurement 56(3): 840-855 (2007)
71		Wei Pei, Wen-Ben Jone, Yiming Hu: Fault Modeling and Detection for Drowsy SRAM Caches. IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1084-1100 (2007)
	2006
70		Ming Li, Qing-An Zeng, Wen-Ben Jone: DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip. DAC 2006: 849-852
69		Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone: Reliability Analysis of Self-Repairable MEMS Accelerometer. DFT 2006: 236-244
68		Ming Li, Wen-Ben Jone, Qing-An Zeng: An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing. ISVLSI 2006: 147-152
67		Wei Pei, Wen-Ben Jone, Yiming Hu: Fault Modeling and Detection for Drowsy SRAM Caches. ITC 2006: 1-10
66		Jianxun Liu, Wen-Ben Jone, Sunil R. Das: Crosstalk test pattern generation for dynamic programmable logic arrays. IEEE T. Instrumentation and Measurement 55(4): 1288-1302 (2006)
	2005
65		Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone: Design and design automation of rectification logic for engineering change. ASP-DAC 2005: 1006-1009
64		Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone: Design and Analysis of Self-Repairable MEMS Accelerometer. DFT 2005: 21-32
63		Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu: Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using concept of sequence characterization. IEEE T. Instrumentation and Measurement 54(5): 1662-1677 (2005)
62		Vinod Narayanan, Swaroop Ghosh, Wen-Ben Jone, Sunil R. Das: A built-in self-testing method for embedded multiport memory arrays. IEEE T. Instrumentation and Measurement 54(5): 1721-1738 (2005)
61		Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone: A dual-mode built-in self-test technique for capacitive MEMS devices. IEEE T. Instrumentation and Measurement 54(5): 1739-1750 (2005)
60		Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu: Fault simulation and response compaction in full scan circuits using HOPE. IEEE T. Instrumentation and Measurement 54(6): 2310-2328 (2005)
	2004
59		Swaroop Ghosh, K. W. Lai, Wen-Ben Jone, Shih-Chieh Chang: Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits. Asian Test Symposium 2004: 210-215
58		Rui Min, Wen-Ben Jone, Yiming Hu: Phased tag cache: an efficient low power cache system. ISCAS (2) 2004: 805-808
57		Rui Min, Wen-Ben Jone, Yiming Hu: Location cache: a low-power L2 cache system. ISLPED 2004: 120-125
56		Rui Min, Zhiyong Xu, Yiming Hu, Wen-Ben Jone: Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs. VLSI Design 2004: 183-188
55		Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone: A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices. VTS 2004: 148-153
54		Vikram Arora, Wen-Ben Jone, Der-Cheng Huang, Sunil R. Das: A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays. IEEE T. Instrumentation and Measurement 53(4): 915-932 (2004)
	2003
53		Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen: Design theory and implementation for low-power segmented bus systems. ACM Trans. Design Autom. Electr. Syst. 8(1): 38-54 (2003)
52		Sunil R. Das, M. Sudarma, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Krishnendu Chakrabarty, Mehmet Sahinoglu: Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets. IEEE T. Instrumentation and Measurement 52(5): 1363-1380 (2003)
51		Wen-Ben Jone, Der-Chen Huang, Sunil R. Das: An efficient BIST method for non-traditional faults of embedded memory arrays. IEEE T. Instrumentation and Measurement 52(5): 1381-1390 (2003)
50		J. H. Jiang, Wen-Ben Jone, Shih-Chieh Chang, Swaroop Ghosh: Embedded core test generation using broadcast test architecture and netlist scrambling. IEEE Transactions on Reliability 52(4): 435-443 (2003)
	2002
49		Sunil R. Das, Jing Yi Liang, Emil M. Petriu, Mansour H. Assaf, Wen-Ben Jone, Krishnendu Chakrabarty: Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering. IEEE T. Instrumentation and Measurement 51(1): 150-172 (2002)
48		Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee: An efficient BIST method for distributed small buffers. IEEE Trans. VLSI Syst. 10(4): 512-515 (2002)
47		Der-Cheng Huang, Wen-Ben Jone: A parallel built-in self-diagnostic method for embedded memoryarrays. IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 449-465 (2002)
46		Der-Cheng Huang, Wen-Ben Jone: A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 617-628 (2002)
	2001
45		J. H. Jiang, Shih-Chieh Chang, Wen-Ben Jone: Embedded Core Testing Using Broadcast Test Architecture. DFT 2001: 95-103
44		Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das: An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers. VLSI Design 2001: 379-384
43		Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das: A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers. VLSI Design 2001: 397-402
42		Wen-Ben Jone, Wu-Sung Yeh, Chingwei Yeh, Sunil R. Das: An adaptive path selection method for delay testing. IEEE T. Instrumentation and Measurement 50(5): 1109-1118 (2001)
41		Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone: Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities. IEEE T. Instrumentation and Measurement 50(6): 1725-1747 (2001)
40		Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang: Charge-sharing alleviation and detection for CMOS domino circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 266-280 (2001)
	2000
39		Der-Cheng Huang, Wen-Ben Jone: An efficient parallel transparent diagnostic BIST. Asian Test Symposium 2000: 299-
38		Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang: Charge sharing fault analysis and testing for CMOS domino logic circuits. Asian Test Symposium 2000: 435-440
37		Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone: Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. DFT 2000: 329-337
36		Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang: Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. ICCAD 2000: 387-390
35		Shih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang: TAIR: testability analysis by implication reasoning. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 152-160 (2000)
	1999
34		Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone: Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications. DAC 1999: 68-71
33		Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone: Charge Sharing Fault Detection for CMOS Domino Logic Circuits. DFT 1999: 77-85
32		Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone: Power reduction through iterative gate sizing and voltage scaling. ISCAS (1) 1999: 246-249
31		Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee: An Efficient BIST Method for Small Buffers. VTS 1999: 246-251
30		J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, Tien-Fu Chen: Segmented bus design for low-power systems. IEEE Trans. VLSI Syst. 7(1): 25-29 (1999)
	1998
29		Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu: A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. ITC 1998: 322-330
28		Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai: A novel combinational testability analysis by considering signal correlation. ITC 1998: 658-667
27		Wen-Ben Jone, Sunil R. Das: A Stochastic Method for Defect Level Analysis of Pseudorandom Testing. VLSI Design 1998: 382-
26		Wen-Ben Jone, K. S. Tsai: Confidence analysis for defect-level estimation of VLSI random testing. ACM Trans. Design Autom. Electr. Syst. 3(3): 389-407 (1998)
	1997
25		Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das: Delay Fault Coverage Enhancement Using Multiple Test Observation Times. VLSI Design 1997: 106-110
24		Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das: Delay Fault Coverage Enhancement Using Variable Observation Times. J. Electronic Testing 11(2): 131-146 (1997)
	1996
23		Sunil R. Das, N. Goel, Wen-Ben Jone, Amiya R. Nayak: Syndrome signature in output compaction for VLSI BIST. VLSI Design 1996: 337-338
22		Dan Li, Wen-Ben Jone: Pseudorandom test-length analysis using differential solutions. IEEE Trans. on CAD of Integrated Circuits and Systems 15(7): 815-825 (1996)
	1995
21		Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak: An improved output compaction technique for built-in self-test in VLSI circuits. VLSI Design 1995: 403-407
20		Wen-Ben Jone, Paresh Gondalia, Allan Gutjahr: Realizing a high measure of confidence for defect level analysis of random testing [VLSI]. IEEE Trans. VLSI Syst. 3(3): 446-450 (1995)
19		Chen-Liang Fang, Wen-Ben Jone: Timing optimization by gate resizing and critical path identification. IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 201-217 (1995)
18		Wen-Ben Jone, Christos A. Papachristou: A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 374-384 (1995)
17		Sunil R. Das, Wen-Ben Jone, Amiya R. Nayak, Ian Choi: On testing of sequential machines using circuit decomposition and stochastic modeling. IEEE Transactions on Systems, Man, and Cybernetics 25(3): 489-504 (1995)
16		Wen-Ben Jone, Sunil R. Das: CACOP-a random pattern testability analyzer. IEEE Transactions on Systems, Man, and Cybernetics 25(5): 865-871 (1995)
	1994
15		Amiya R. Nayak, Wen-Ben Jone, Sunil R. Das: Designing General-Purpose Fault-Tolerant Distributed Systems - A Layered Approach. ICPADS 1994: 360-365
14		Sunil R. Das, Wen-Ben Jone, Amiya Nayak, Ian Choi: On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition. VLSI Design 1994: 311-314
13		Wen-Ben Jone, Cheng-Juei Wu: Multiple Fault Detection in Parity Checkers. IEEE Trans. Computers 43(9): 1096-1099 (1994)
	1993
12		Wen-Ben Jone, Chen-Liang Fang: Timing Optimization By Gate Resizing And Critical Path Identification. DAC 1993: 135-140
11		Cheng-Juei Wu, Wen-Ben Jone: On Multiple Fault Detection of Parity Checkers. ISCAS 1993: 1515-1518
10		Paresh Gondalia, Allan Gutjahr, Wen-Ben Jone: Realizing a High Measure of Confidence for Defect Level Analysis of Random Testing. ITC 1993: 478-487
9		Wen-Ben Jone, Sunil R. Das: CACOP - A Random Pattern Testability Analyzer. VLSI Design 1993: 61-64
8		Wen-Ben Jone, Patrick H. Madden: Multiple fault testing using minimal single fault test set for fanout-free circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 149-157 (1993)
7		Wen-Ben Jone: Defect level estimation of circuit testing using sequential statistical analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(2): 336-348 (1993)
	1991
6		Anita Gleason, Wen-Ben Jone: Reduced Hamming Count and Its Aliasing Probability. ICCD 1991: 356-359
5		Wen-Ben Jone: Defect Level Estimation of Random and Pseudorandom Testing. ITC 1991: 712-721
4		Wen-Ben Jone, Anita Gleason: Analysis of Hamming count compaction scheme. J. Electronic Testing 2(4): 373-384 (1991)
	1990
3		Wen-Ben Jone, Sunil R. Das: Multiple-output parity bit signature for exhaustive testing. J. Electronic Testing 1(2): 175-178 (1990)
	1989
2		Wen-Ben Jone, Christos A. Papachristou: A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing. DAC 1989: 525-534
1		Wen-Ben Jone, Christos A. Papachristou, M. Pereira: A Scheme for Overlaying Concurrent Testing of VLSI Circuits. DAC 1989: 531-536

Coauthor Index

1	Ravi Apte	[75] [81]
2	Vikram Arora	[54]
3	Mansour H. Assaf	[41] [49] [52] [60] [63] [72] [74]
4	Satyendra Biswas	[72] [74]
5	Krishnendu Chakrabarty	[49] [52]
6	Min-Cheng Chang	[32] [34]
7	Shi-Sen Chang	[28] [35]
8	Shih-Chieh Chang	[28] [29] [32] [33] [34] [35] [36] [37] [38] [40] [45] [50] [59] [65]
9	Hao-Jan Chao	[75] [81] [88]
10	J.-Y. Chen	[30] [53]
11	Tien-Fu Chen	[30]
12	Ching-Hwa Cheng	[33] [36] [37] [38] [40]
13	Ian Choi	[14] [17]
14	Sunil R. Das	[3] [9] [14] [15] [16] [17] [21] [23] [24] [25] [27] [41] [42] [43] [44] [49] [51] [52] [54] [60] [62] [63] [66] [72] [74]
15	Chen-Liang Fang	[12] [19]
16	Hiroshi Furukawa	[88]
17	Swaroop Ghosh	[50] [59] [62]
18	Anita Gleason	[4] [6]
19	N. Goel	[23]
20	Paresh Gondalia	[10] [20]
21	Jianghao Guo	[75] [81] [88]
22	Allan Gutjahr	[10] [20]
23	H. T. Ho	[21]
24	Yun-Pan Ho	[24] [25]
25	Altaf Hossain	[74]
26	Michael S. Hsiao	[92]
27	I. P. Hsu	[53]
28	Yiming Hu	[56] [57] [58] [67] [71] [95]
29	Yu Hu	[92]
30	Der-Chen Huang	[51]
31	Der-Cheng Huang	[31] [39] [43] [44] [46] [47] [48] [54]
32	Jiun-Lang Huang	[92]
33	Yung-Chang Huang	[65]
34	J. H. Jiang	[45] [50]
35	Zhigang Jiang	[92]
36	Hyoung-Kook Kim	[83] [85] [87]
37	K. W. Lai	[59]
38	Kuen-Jong Lee	[31] [48] [75] [81]
39	Shin-De Lee	[40]
40	Chien-Mo James Li (James Chien-Mo Li, J. C.-M. Li)	[92]
41	Dan Li	[22]
42	Fangfang Li	[75] [81]
43	Ming Li	[68] [70]
44	Shin-De Li	[36]
45	Jing Yi Liang	[49]
46	Cheng-Hung Lin	[65]
47	Jianxun Liu	[66] [73]
48	Jinsong Liu	[75] [81]
49	Hsueh-I Lu	[30] [53]
50	Patrick H. Madden	[8]
51	Rui Min	[56] [57] [58] [95]
52	Vinod Narayanan	[62]
53	Amiya Nayak (Amiya R. Nayak)	[14] [15] [17] [21] [23] [72]
54	Jason Nemeth	[95]
55	Yanlong Niu	[75] [81]
56	Christos A. Papachristou	[1] [2] [18]
57	Wei Pei	[67] [71]
58	M. Pereira	[1]
59	Emil M. Petriu	[41] [49] [52] [60] [63] [72] [74]
60	C. V. Ramamoorthy (Chittoor V. Ramamoorthy)	[41] [60] [63]
61	Jiann-Chyi Rau	[29]
62	Mehmet Sahinoglu	[52] [60] [63] [72] [74]
63	Boryau Sheu	[75] [81] [88]
64	M. Sudarma	[52]
65	Yi-Chih Sung	[75] [81]
66	Lang Tan	[92]
67	Chien-Chung Tsai	[28]
68	K. S. Tsai	[26]
69	Ranga Vemuri	[76] [77] [78] [82] [84] [86] [89] [90] [91] [93] [94]
70	Chi-Chun Wang	[75] [81]
71	Jinn-Shyan Wang	[30] [33] [36] [37] [38] [40] [53]
72	Laung-Terng Wang	[75] [81] [83] [85] [87] [88] [92]
73	Wei-Shin Wang	[75] [81]
74	Xiaoqing Wen	[75] [81] [88] [92]
75	Cheng-Juei Wu	[11] [13]
76	S. C. Wu	[31] [48]
77	Shianling Wu	[75] [81] [85] [88] [92]
78	Yu-Liang Wu (David Yu-Liang Wu)	[29] [55] [61] [64] [69] [79] [80]
79	Xingguo Xiong	[55] [61] [64] [69] [79] [80]
80	Hao Xu	[76] [77] [78] [82] [84] [86] [89] [90] [91] [93] [94]
81	Zhiyong Xu	[56]
82	Chia-Hsien Yeh	[75]
83	Chingwei Yeh (Ching-Wei Yeh)	[32] [34] [42]
84	Wu-Sung Yeh	[42]
85	Lizhen Yu	[92]
86	Jila Zakizadeh	[72]
87	Qing-An Zeng	[68] [70]
88	Yu Zhang	[92]

Colors in the list of coauthors

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