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Eugene B. John
List of publications from the DBLP Bibliography Server - FAQ
| 2011 | ||
|---|---|---|
| 25 | P. S. Nair, Dhireesha Kudithipudi, Eugene B. John, Fred W. Hudson: Execution characteristics of embedded applications on a Pentium 4-based personal computer. J. Embedded Computing 4(3-4): 107-116 (2011) | |
| 2010 | ||
| 24 | Savithra Eratne, Claudia Romo, Eugene John, Byeong Kil Lee: Leakage and Access Time Tradeoffs for Cache in High Performance Microprocessors. CDES 2010: 105-108 | |
| 23 | Byeong Kil Lee, Satish Raghunath, Eugene John: Architectural Sensitivity Analysis on Network Workloads. CDES 2010: 140-145 | |
| 22 | Savithra Eratne, Claudia Romo, Eugene John: Leakage Power Analysis of Multi-bit Adders Using Transistor Gate Length Increase. CDES 2010: 61-66 | |
| 21 | Binu P. John, Abhishek Agrawal, Bob Steigerwald, Eugene B. John: Impact of Operating System Behavior on Battery Life. J. Low Power Electronics 6(1): 10-17 (2010) | |
| 2009 | ||
| 20 | Binu P. John, Pradeep Nair, Eugene John, Fred W. Hudson: Performance Measurement of Single, Dual and Quad Core Machines Using SPEC CPU2006. CDES 2009: 143-149 | |
| 19 | Ciji Isen, Lizy K. John, Eugene John: A Tale of Two Processors: Revisiting the RISC-CISC Debate. SPEC Benchmark Workshop 2009: 57-76 | |
| 18 | Christopher Martinez, Mythri Pinnamaneni, Eugene B. John: Performance of commercial multimedia workloads on the Intel Pentium 4: A case study. Computers & Electrical Engineering 35(1): 18-32 (2009) | |
| 17 | Dhireesha Kudithipudi, Eugene John: Implications of gated-Vss technique on leakage power in embedded caches. IJES 4(1): 17-26 (2009) | |
| 2008 | ||
| 16 | Pradeep Nair, Savithra Eratne, Eugene John: Effects of Register File Organization on Leakage Power Consumption. CDES 2008: 85-88 | |
| 15 | Savithra Eratne, Sebastian Puthenpurayil, Eugene John: Energy Efficiency of Data Compression with Wavelets. IPCV 2008: 75-78 | |
| 14 | Christopher B. Smith, David R. Mandel, Eugene John: A superscalar simulation employing poisson distributed stalls. Computers & Electrical Engineering 34(3): 192-201 (2008) | |
| 13 | Dhireesha Kudithipudi, Stefan Petko, Eugene B. John: Caches for Multimedia Workloads: Power and Energy Tradeoffs. IEEE Transactions on Multimedia 10(6): 1013-1021 (2008) | |
| 2007 | ||
| 12 | Pradeep Nair, Eugene John: Performance Analysis of an Intel Pentium-4 Based Personal Computer for Multiplke Sequence Alignment. CDES 2007: 74-77 | |
| 11 | Pradeep S. Nair, Eugene B. John: Analysing the performance of personal computers based on Intel microprocessors for sequence aligning bioinformatics applications. IJBRA 3(2): 187-205 (2007) | |
| 10 | Dhireesha Kudithipudi, Eugene John: Static Power Analysis and Estimation in Ternary Content Addressable Memory Cells. J. Low Power Electronics 3(3): 293-301 (2007) | |
| 2006 | ||
| 9 | Pradeep Nair, Eugene John: Performance of Sequence Alignment Bioinformatics Applications on General Purpose Processors: A Case Study. BIOCOMP 2006: 556-559 | |
| 8 | Pradeep Nair, Dhireesha Kudithipudi, Eugene John, Fred W. Hudson: Performance Analysis of Embedded Applications on a Pentium-4 Based Machine. ESA 2006: 191-197 | |
| 7 | Byeong Kil Lee, Lizy Kurian John, Eugene John: Architectural enhancements for network congestion control applications. IEEE Trans. VLSI Syst. 14(6): 609-615 (2006) | |
| 2005 | ||
| 6 | Byeong Kil Lee, Lizy Kurian John, Eugene John: Architectural Support for Accelerating Congestion Control Applications in Network Processors. ASAP 2005: 169-178 | |
| 5 | Dhireesha Kudithipudi, Eugene John: Parametrical characterization of leakage power in embedded system caches using gated-VSS. Circuits, Signals, and Systems 2005: 308-312 | |
| 4 | Dhireesha Kudithipudi, Eugene John: Implementation of Low Power Digital Multipliers using 10 -Transistor Adder Blocks. J. Low Power Electronics 1(3): 286-296 (2005) | |
| 2004 | ||
| 3 | Dhireesha Kudithipudi, R. Kotha, Eugene John, Z. Pantic-Tanner: Impact of nanotechnology on the performance of CMOS digital multipliers. Circuits, Signals, and Systems 2004: 439-442 | |
| 1999 | ||
| 2 | R. Shalem, Lizy Kurian John, Eugene John: A Novel Low Power Energy Recovery Full Adder Cell. Great Lakes Symposium on VLSI 1999: 380- | |
| 1995 | ||
| 1 | Lizy Kurian John, Daniel Brewer, Eugene John: Design of a highly reconfigurable interconnect for array processors. VLSI Design 1995: 321-325 | |
| 1 | Abhishek Agrawal | [21] |
| 2 | Daniel Brewer | [1] |
| 3 | Savithra Eratne | [15] [16] [22] [24] |
| 4 | Fred W. Hudson | [8] [20] [25] |
| 5 | Ciji Isen | [19] |
| 6 | Binu P. John | [20] [21] |
| 7 | Lizy Kurian John (Lizy K. John) | [1] [2] [6] [7] [19] |
| 8 | R. Kotha | [3] |
| 9 | Dhireesha Kudithipudi | [3] [4] [5] [8] [10] [13] [17] [25] |
| 10 | Byeong Kil Lee | [6] [7] [23] [24] |
| 11 | David R. Mandel | [14] |
| 12 | Christopher Martinez | [18] |
| 13 | P. S. Nair | [25] |
| 14 | Pradeep Nair | [8] [9] [12] [16] [20] |
| 15 | Pradeep S. Nair | [11] |
| 16 | Z. Pantic-Tanner | [3] |
| 17 | Stefan Petko | [13] |
| 18 | Mythri Pinnamaneni | [18] |
| 19 | Sebastian Puthenpurayil | [15] |
| 20 | Satish Raghunath | [23] |
| 21 | Claudia Romo | [22] [24] |
| 22 | R. Shalem | [2] |
| 23 | Christopher B. Smith | [14] |
| 24 | Bob Steigerwald | [21] |
Colors in the list of coauthors
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