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| 2010 | ||
|---|---|---|
| 4 | Yung-Chuan Jiang, Jhing-Fa Wang: Reduced Communication Costs via Network Flow and Scheduling for Partitions of Dynamically Reconfigurable FPGAs. J. Inf. Sci. Eng. 26(2): 565-583 (2010) | |
| 3 | Anand Paul, Yung-Chuan Jiang, Jhing-Fa Wang: Computation Aware Scheme for Visual Signal Processing. JSW 5(6): 573-578 (2010) | |
| 2007 | ||
| 2 | Yung-Chuan Jiang, Jhing-Fa Wang: Temporal Partitioning Data Flow Graphs for Dynamically Reconfigurable Computing. IEEE Trans. VLSI Syst. 15(12): 1351-1361 (2007) | |
| 2005 | ||
| 1 | Yen-Tai Lai, Yung-Chuan Jiang, Hong-Ming Chu: BDD decomposition for mixed CMOS/PTL logic circuit synthesis. ISCAS (6) 2005: 5649-5652 | |
| 1 | Hong-Ming Chu | [1] |
| 2 | Yen-Tai Lai | [1] |
| 3 | Anand Paul | [3] |
| 4 | Jhing-Fa Wang | [2] [3] [4] |
Colors in the list of coauthors
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