Yanbin Jiang

	2001
4		Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji: Technology mapping for high-performance static CMOS and pass transistor logic designs. IEEE Trans. VLSI Syst. 9(5): 577-589 (2001)
	1999
3		Yanbin Jiang, Sachin S. Sapatnekar: An integrated algorithm for combined placement and libraryless technology mapping. ICCAD 1999: 102-106
	1998
2		Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim: Interleaving buffer insertion and transistor sizing into a single optimization. IEEE Trans. VLSI Syst. 6(4): 625-633 (1998)
	1997
1		Juho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar: Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs. ISPD 1997: 130-135

Coauthor Index

1	Cyrus Bamji	[1] [2] [4]
2	Juho Kim	[1] [2]
3	Sachin S. Sapatnekar	[1] [2] [3] [4]

Last update Sat Jun 2 20:57:36 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page