 | 2011 |
|---|
| 7 |       | Kuo-Hsing Cheng,
Jen-Chieh Liu,
Chih-Yu Chang,
Shu-Yu Jiang,
Kai-Wei Hong:
Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator.
IEEE Trans. VLSI Syst. 19(8): 1325-1335 (2011) |
| 2009 |
|---|
| 6 | | Shu-Yu Jiang,
Kuo-Hsing Cheng,
Pei-Yi Jian:
A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver.
IEEE Trans. VLSI Syst. 17(12): 1698-1708 (2009) |
| 5 | | Shu-Yu Jiang,
Chan-Wei Huang,
Yu-lung Lo,
Kuo-Hsing Cheng:
Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System.
IEICE Transactions 92-A(2): 389-400 (2009) |
| 2006 |
|---|
| 4 | | Kuo-Hsing Cheng,
Chan-Wei Huang,
Shu-Yu Jiang:
Self-sampled vernier delay line for built-in clock jitter measurement.
ISCAS 2006 |
| 2005 |
|---|
| 3 | | Kuo-Hsing Cheng,
Shu-Ming Chang,
Shu-Yu Jiang,
Wei-Bin Yang:
A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit.
ISCAS (2) 2005: 1174-1177 |
| 2004 |
|---|
| 2 |  | Kuo-Hsing Cheng,
Chia-Hung Wei,
Shu-Yu Jiang:
Static divided word matching line for low-power Content Addressable Memory design.
ISCAS (2) 2004: 629-632 |
| 2003 |
|---|
| 1 | | Kuo-Hsing Cheng,
Shu-Yu Jiang,
Zong-Shen Chen:
BIST for clock jitter measurements.
ISCAS (5) 2003: 577-580 |
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