Jian Hong Jiang

	2009
2		Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone: A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control. ISSCC 2009: 188-189
	2007
1		Jian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone: Design Consideration of 6.25 Gbps Signaling for High-Performance Server. ASP-DAC 2007: 854-857

Coauthor Index

1	Weixin Gai	[1] [2]
2	Akira Hattori	[1]
3	Yasuo Hidaka	[1] [2]
4	Takeshi Horie	[1] [2]
5	Yoichi Koyanagi	[1] [2]
6	Hideki Osone	[1] [2]

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