 | 2012 |
|---|
| 30 |       | Yen-Ting Yu,
Ya-Chung Chan,
Subarna Sinha,
Iris Hui-Ru Jiang,
Charles Chiang:
Accurate process-hotspot detection using critical design rule extraction.
DAC 2012: 1167-1172 |
| 29 | | Hua-Yu Chang,
Iris Hui-Ru Jiang,
Yao-Wen Chang:
Timing ECO optimization using metal-configurable gate-array spare cells.
DAC 2012: 802-807 |
| 28 | | Jing-Wei Lin,
Tsung-Yi Ho,
Iris Hui-Ru Jiang:
Reliability-Driven Power/Ground Routing for Analog ICs.
ACM Trans. Design Autom. Electr. Syst. 17(1): 6 (2012) |
| 27 | | Iris Hui-Ru Jiang,
Hua-Yu Chang:
ECOS: Stable Matching Based Metal-Only ECO Synthesis.
IEEE Trans. VLSI Syst. 20(3): 485-497 (2012) |
| 26 | | Iris Hui-Ru Jiang,
Hua-Yu Chang,
Chih-Long Chang:
WiT: Optimal Wiring Topology for Electromigration Avoidance.
IEEE Trans. VLSI Syst. 20(4): 581-592 (2012) |
| 25 | | Iris Hui-Ru Jiang,
Chih-Long Chang,
Yu-Ming Yang:
INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving.
IEEE Trans. on CAD of Integrated Circuits and Systems 31(2): 192-204 (2012) |
| 2011 |
|---|
| 24 | | Hua-Yu Chang,
Iris Hui-Ru Jiang,
Yao-Wen Chang:
Simultaneous functional and timing ECO.
DAC 2011: 140-145 |
| 23 | | Hua-Yu Chang,
Iris Hui-Ru Jiang,
Yao-Wen Chang:
Timing ECO optimization via Bézier curve smoothing and fixability identification.
ICCAD 2011: 742-746 |
| 22 | | Iris Hui-Ru Jiang,
Chih-Long Chang,
Yu-Ming Yang,
Evan Y.-W. Tsai,
Lancer S.-F. Chen:
INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs.
ISPD 2011: 115-122 |
| 21 | | Cheng-Chi Chan,
Yen-Ting Yu,
Iris Hui-Ru Jiang:
3DICE: 3D IC cost evaluation based on fast tier number estimation.
ISQED 2011: 50-55 |
| 2010 |
|---|
| 20 | | Iris Hui-Ru Jiang,
Hua-Yu Chang:
Live Demo: ECOS 1.0: A metal-only ECO synthesizer.
ISCAS 2010: 2774 |
| 19 | | Iris Hui-Ru Jiang,
Hua-Yu Chang,
Chih-Long Chang:
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles.
ISPD 2010: 177-184 |
| 18 | | Yu-Ming Yang,
Iris Hui-Ru Jiang:
Analog placement and global routing considering wiring symmetry.
ISQED 2010: 618-623 |
| 17 | | Houng-Yi Li,
Iris Hui-Ru Jiang,
Hung-Ming Chen:
Simultaneous voltage island generation and floorplanning.
SoCC 2010: 219-223 |
| 2009 |
|---|
| 16 | | Wan-Yu Lee,
Iris Hui-Ru Jiang:
VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power.
ACM Great Lakes Symposium on VLSI 2009: 39-44 |
| 15 | | Iris Hui-Ru Jiang,
Hua-Yu Chang,
Liang-Gi Chang,
Huang-Bi Hung:
Matching-based minimum-cost spare cell selection for design changes.
DAC 2009: 408-411 |
| 14 | | Iris Hui-Ru Jiang,
Ming-Hua Wu:
POSA: Power-state-aware Buffered Tree Construction.
ISCAS 2009: 787 |
| 13 | | Iris Hui-Ru Jiang:
Generic integer linear programming formulation for 3D IC partitioning.
SoCC 2009: 321-324 |
| 2008 |
|---|
| 12 | | Iris Hui-Ru Jiang,
Ming-Hua Wu:
Power-state-aware buffered tree construction.
ICCD 2008: 21-26 |
| 11 | | Iris Hui-Ru Jiang,
Yen-Ting Yu:
Configurable rectilinear Steiner tree construction for SoC and nano technologies.
ICCD 2008: 34-39 |
| 10 | | Iris Hui-Ru Jiang,
Shung-Wei Lin,
Yen-Ting Yu:
Unification of obstacle-avoiding rectilinear Steiner tree construction.
SoCC 2008: 127-130 |
| 2006 |
|---|
| 9 | | Iris Hui-Ru Jiang,
Song-Ra Pan,
Yao-Wen Chang,
Jing-Yang Jou:
Reliable crosstalk-driven interconnect optimization.
ACM Trans. Design Autom. Electr. Syst. 11(1): 88-103 (2006) |
| 2004 |
|---|
| 8 | | Iris Hui-Ru Jiang,
Yao-Wen Chang,
Jing-Yang Jou,
Kai-Yuan Chao:
Simultaneous floor plan and buffer-block optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 694-703 (2004) |
| 2002 |
|---|
| 7 | | Nicholas Chia-Yuan Chang,
Yao-Wen Chang,
Iris Hui-Ru Jiang:
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning.
ISQED 2002: 523-528 |
| 2000 |
|---|
| 6 | | Iris Hui-Ru Jiang,
Song-Ra Pan,
Yao-Wen Chang,
Jing-Yang Jou:
Optimal reliable crosstalk-driven interconnect optimization.
ISPD 2000: 128-133 |
| 5 | | Iris Hui-Ru Jiang,
Yao-Wen Chang,
Jing-Yang Jou:
Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 999-1010 (2000) |
| 1999 |
|---|
| 4 | | Jiann-Horng Lin,
Jing-Yang Jou,
Iris Hui-Ru Jiang:
Hierarchical Floorplan Design on the Internet.
ASP-DAC 1999: 189-192 |
| 3 | | Iris Hui-Ru Jiang,
Jing-Yang Jou,
Yao-Wen Chang:
Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation.
DAC 1999: 90-95 |
| 2 | | Mango Chia-Tso Chao,
Guang-Ming Wu,
Iris Hui-Ru Jiang,
Yao-Wen Chang:
A clustering- and probability-based approach for time-multiplexed FPGA partitioning.
ICCAD 1999: 364-369 |
| 1 | | Jie-Hong Roland Jiang,
Iris Hui-Ru Jiang:
Optimum loading dispersion for high-speed tree-type decision circuitry.
ICCAD 1999: 520-525 |
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