| | |
- CSB - MetaPress - Google - Bing - Yahoo
 | 2012 | |
|---|---|---|
| 306 |      | Mohammed Shoaib, Niraj K. Jha, Naveen Verma: Enabling advanced inference on sensor nodes through direct use of compressively-sensed signals. DATE 2012: 437-442 |
| 305 | | Sourindra Chaudhuri, Prateek Mishra, Niraj K. Jha: Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology. VLSI Design 2012: 238-244 |
| 304 | | Chunxiao Li, Niraj K. Jha, Anand Raghunathan: Secure reconfiguration of software-defined radio. ACM Trans. Embedded Comput. Syst. 11(1): 10 (2012) |
| 2011 | ||
| 303 | | Mohammed Shoaib, Niraj K. Jha, Naveen Verma: A low-energy computation platform for data-driven biomedical monitoring algorithms. DAC 2011: 591-596 |
| 302 | | Chun-Yi Lee, Niraj K. Jha: CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations. DAC 2011: 866-871 |
| 301 | | Sourindra Chaudhuri, Niraj K. Jha: 3D vs. 2D analysis of FinFET logic gates under process variations. ICCD 2011: 435-436 |
| 300 | | Ajay N. Bhoj, Niraj K. Jha: Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology. ISQED 2011: 695-702 |
| 299 | | Najwa Aaraj, Anand Raghunathan, Niraj K. Jha: A framework for defending embedded systems against software attacks. ACM Trans. Embedded Comput. Syst. 10(3): 33 (2011) |
| 298 | | Meng Zhang, Niraj K. Jha: FinFET-Based Power Management for Improved DPA Resistance with Low Overhead. JETC 7(3): 10 (2011) |
| 2010 | ||
| 297 | | Chunxiao Li, Anand Raghunathan, Niraj K. Jha: A Secure User Interface for Web Applications Running Under an Untrusted Operating System. CIT 2010: 865-870 |
| 296 | | Prateek Mishra, Niraj K. Jha: Low-power FinFET circuit synthesis using surface orientation optimization. DATE 2010: 311-314 |
| 295 | | Chunxiao Li, Anand Raghunathan, Niraj K. Jha: Secure Virtual Machine Execution under an Untrusted Management OS. IEEE CLOUD 2010: 172-179 |
| 294 | | Prateek Mishra, Ajay N. Bhoj, Niraj K. Jha: Die-level leakage power analysis of FinFET circuits considering process variations. ISQED 2010: 347-355 |
| 293 | | Niraj K. Jha: Editorial: New Associate Editor Appointments. IEEE Trans. VLSI Syst. 18(3): 345-346 (2010) |
| 292 | | Chun-Yi Lee, Niraj K. Jha: FinFET-based power simulator for interconnection networks. JETC 6(1): (2010) |
| 291 | | Wei Zhang, Niraj K. Jha, Li Shang: Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture. JETC 6(3): (2010) |
| 290 | | Ajay N. Bhoj, Niraj K. Jha: Gated-diode FinFET DRAMs: Device and circuit design-considerations. JETC 6(4): 12 (2010) |
| 2009 | ||
| 289 | | Chunxiao Li, Anand Raghunathan, Niraj K. Jha: An architecture for secure software defined radio. DATE 2009: 448-453 |
| 288 | | Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha: In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects. HPCA 2009: 67-78 |
| 287 | | Chun-Yi Lee, Niraj K. Jha: FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing. ICCD 2009: 350-357 |
| 286 | | Ajay N. Bhoj, Niraj K. Jha: Pragmatic design of gated-diode FinFET DRAMs. ICCD 2009: 390-397 |
| 285 | | Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha: GARNET: A detailed on-chip network model inside a full-system simulator. ISPASS 2009: 33-42 |
| 284 | | Muzaffer O. Simsir, Niraj K. Jha: Thermal characterization of BIST, scan design and sequential test methodologies. ITC 2009: 1-9 |
| 283 | | Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha: In-network coherence filtering: snoopy coherence without broadcasts. MICRO 2009: 232-243 |
| 282 | | Niraj K. Jha: Editorial Appointments for the 2009-2010 Term. IEEE Trans. VLSI Syst. 17(4): 453-469 (2009) |
| 281 | | Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty: Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits. IEEE Trans. VLSI Syst. 17(5): 697-708 (2009) |
| 280 | | Prateek Mishra, Anish Muttreja, Niraj K. Jha: Low-power FinFET circuit synthesis using multiple supply and threshold voltages. JETC 5(2): (2009) |
| 279 | | Wei Zhang, Niraj K. Jha, Li Shang: A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow. JETC 5(3): (2009) |
| 278 | | Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha: A hybrid nano-CMOS architecture for defect and fault tolerance. JETC 5(3): (2009) |
| 277 | | Wei Zhang, Niraj K. Jha, Li Shang: A hybrid nano/CMOS dynamically reconfigurable system - Part I: Architecture. JETC 5(4): (2009) |
| 276 | | Wei Zhang, Niraj K. Jha, Li Shang: Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture. JETC 5(4): (2009) |
| 2008 | ||
| 275 | | Najwa Aaraj, Anand Raghunathan, Niraj K. Jha: Dynamic Binary Instrumentation-Based Framework for Malware Defense. DIMVA 2008: 64-87 |
| 274 | | Amit Kumar, Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha: A system-level perspective for efficient NoC design. IPDPS 2008: 1-5 |
| 273 | | Amit Kumar, Li-Shiuan Peh, Niraj K. Jha: Token flow control. MICRO 2008: 342-353 |
| 272 | | Anish Muttreja, Prateek Mishra, Niraj K. Jha: Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects. VLSI Design 2008: 220-227 |
| 271 | | Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha: Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture. VLSI Design 2008: 435-440 |
| 270 | | Anish Muttreja, Srivaths Ravi, Niraj K. Jha: Variability-Tolerant Register-Transfer Level Synthesis. VLSI Design 2008: 621-628 |
| 269 | | Yunsi Fei, Lin Zhong, Niraj K. Jha: An energy-aware framework for dynamic software management in mobile computing systems. ACM Trans. Embedded Comput. Syst. 7(3): (2008) |
| 268 | | Najwa Aaraj, Anand Raghunathan, Niraj K. Jha: Analysis and design of a hardware/software trusted platform module for embedded systems. ACM Trans. Embedded Comput. Syst. 8(1): (2008) |
| 267 | | Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha: Toward Ideal On-Chip Communication Using Express Virtual Channels. IEEE Micro 28(1): 80-90 (2008) |
| 266 | | Pallav Gupta, Rui Zhang, Niraj K. Jha: Automatic Test Generation for Combinational Threshold Logic Networks. IEEE Trans. VLSI Syst. 16(8): 1035-1045 (2008) |
| 265 | | Amit Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha: System-Level Dynamic Thermal Management for High-Performance Microprocessors. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 96-108 (2008) |
| 264 | | James Donald, Niraj K. Jha: Reversible logic synthesis with Fredkin and Peres gates. JETC 4(1): (2008) |
| 2007 | ||
| 263 | | Wei Zhang, Li Shang, Niraj K. Jha: NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture. DAC 2007: 300-305 |
| 262 | | Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Energy and execution time analysis of a software-based trusted platform module. DATE 2007: 1128-1133 |
| 261 | | Anish Muttreja, Niket Agarwal, Niraj K. Jha: CMOS logic design with independent-gate FinFETs. ICCD 2007: 560-567 |
| 260 | | Amit Kumar, Partha Kundu, Arvind P. Singh, Li-Shiuan Peh, Niraj K. Jha: A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS. ICCD 2007: 63-70 |
| 259 | | Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha: Express virtual channels: towards the ideal interconnection fabric. ISCA 2007: 150-161 |
| 258 | | Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha: Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits. VLSI Design 2007: 504-512 |
| 257 | | Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Energy-optimizing source code transformations for operating system-driven embedded software. ACM Trans. Embedded Comput. Syst. 7(1): (2007) |
| 256 | | Pallav Gupta, Niraj K. Jha, Loganathan Lingappan: A Test Generation Framework for Quantum Cellular Automata Circuits. IEEE Trans. VLSI Syst. 15(1): 24-36 (2007) |
| 255 | | Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. IEEE Trans. VLSI Syst. 15(11): 1191-1204 (2007) |
| 254 | | Niraj K. Jha: Editorial. IEEE Trans. VLSI Syst. 15(3): 249-261 (2007) |
| 253 | | Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems. IEEE Trans. VLSI Syst. 15(3): 296-308 (2007) |
| 252 | | Jiong Luo, Niraj K. Jha, Li-Shiuan Peh: Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. IEEE Trans. VLSI Syst. 15(4): 427-437 (2007) |
| 251 | | Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee: Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis. IEEE Trans. VLSI Syst. 15(4): 465-470 (2007) |
| 250 | | Loganathan Lingappan, Niraj K. Jha: Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. IEEE Trans. VLSI Syst. 15(5): 518-530 (2007) |
| 249 | | Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Architectural Support for Run-Time Validation of Program Data Properties. IEEE Trans. VLSI Syst. 15(5): 546-559 (2007) |
| 248 | | Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha: Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. IEEE Trans. VLSI Syst. 15(5): 605-609 (2007) |
| 247 | | Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar: Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. IEEE Trans. VLSI Syst. 15(6): 699-710 (2007) |
| 246 | | Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Hybrid Simulation for Energy Estimation of Embedded Software. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1843-1854 (2007) |
| 245 | | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2035-2045 (2007) |
| 244 | | Li Shang, Robert P. Dick, Niraj K. Jha: SLOPES: Hardware-Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 508-526 (2007) |
| 243 | | Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Automated Energy/Performance Macromodeling of Embedded Software. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 542-552 (2007) |
| 242 | | Jiong Luo, Niraj K. Jha: Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1161-1170 (2007) |
| 241 | | Rui Zhang, Pallav Gupta, Niraj K. Jha: Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1233-1245 (2007) |
| 240 | | Loganathan Lingappan, Niraj K. Jha: Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1339-1345 (2007) |
| 2006 | ||
| 239 | | Rui Zhang, Niraj K. Jha: Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations. ACM Great Lakes Symposium on VLSI 2006: 8-13 |
| 238 | | Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Architectural support for safe software execution on embedded processors. CODES+ISSS 2006: 106-111 |
| 237 | | Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar: Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. DAC 2006: 496-501 |
| 236 | | Amit Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha: HybDTM: a coordinated hardware-software approach for dynamic thermal management. DAC 2006: 548-553 |
| 235 | | Wei Zhang, Niraj K. Jha, Li Shang: NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture. DAC 2006: 711-716 |
| 234 | | Pallav Gupta, Niraj K. Jha, Loganathan Lingappan: Test generation for combinational quantum cellular automata (QCA) circuits. DATE 2006: 311-316 |
| 233 | | Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Architectures for efficient face authentication in embedded systems. DATE Designers' Forum 2006: 1-6 |
| 232 | | Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee: Satisfiability-based framework for enabling side-channel attacks on cryptographic software. DATE Designers' Forum 2006: 18-23 |
| 231 | | Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Active Learning Driven Data Acquisition for Sensor Networks. ISCC 2006: 929-934 |
| 230 | | Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha: Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. VLSI Design 2006: 299-304 |
| 229 | | Rui Zhang, Niraj K. Jha: State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies. VLSI Design 2006: 317-322 |
| 228 | | Loganathan Lingappan, Niraj K. Jha: Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults. VLSI Design 2006: 431-436 |
| 227 | | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. VLSI Design 2006: 473-476 |
| 226 | | Li Shang, Li-Shiuan Peh, Amit Kumar, Niraj K. Jha: Temperature-Aware On-Chip Networks. IEEE Micro 26(1): 130-139 (2006) |
| 225 | | Lin Zhong, Niraj K. Jha: Dynamic Power Optimization Targeting User Delays in Interactive Systems. IEEE Trans. Mob. Comput. 5(11): 1473-1488 (2006) |
| 224 | | Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols. IEEE Trans. Mob. Comput. 5(2): 128-143 (2006) |
| 223 | | Keith S. Vallerio, Lin Zhong, Niraj K. Jha: Energy-Efficient Graphical User Interface Design. IEEE Trans. Mob. Comput. 5(7): 846-859 (2006) |
| 222 | | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: A Scalable Synthesis Methodology for Application-Specific Processors. IEEE Trans. VLSI Syst. 14(11): 1175-1188 (2006) |
| 221 | | Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. IEEE Trans. VLSI Syst. 14(12): 1295-1308 (2006) |
| 220 | | Li Shang, Li-Shiuan Peh, Niraj K. Jha: PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 92-110 (2006) |
| 219 | | Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Use of Computation-Unit Integrated Memories in High-Level Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 1969-1989 (2006) |
| 218 | | Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: RTL-Aware Cycle-Accurate Functional Power Estimation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2103-2117 (2006) |
| 217 | | Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar: Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2193-2206 (2006) |
| 216 | | Pallav Gupta, Abhinav Agrawal, Niraj K. Jha: An Algorithm for Synthesis of Reversible Logic Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2317-2330 (2006) |
| 215 | | Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha: Satisfiability-based test generation for nonseparable RTL controller-datapath circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 544-557 (2006) |
| 214 | | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Application-specific heterogeneous multiprocessor synthesis using extensible processors. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1589-1602 (2006) |
| 2005 | ||
| 213 | | Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Enhancing security through hardware-assisted run-time validation of program data properties. CODES+ISSS 2005: 190-195 |
| 212 | | Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Hybrid simulation for embedded software energy estimation. DAC 2005: 23-26 |
| 211 | | Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Efficient fingerprint-based user authentication for embedded systems. DAC 2005: 244-247 |
| 210 | | Le Yan, Lin Zhong, Niraj K. Jha: User-perceived latency driven voltage scaling for interactive applications. DAC 2005: 624-627 |
| 209 | | Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. DATE 2005: 178-183 |
| 208 | | Niraj K. Jha: Nanotechnology in the Service of Embedded and Ubiquitous Computing. EUC 2005: 1 |
| 207 | | Wei Zhang, Niraj K. Jha: ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology. ICCD 2005: 281-288 |
| 206 | | Le Yan, Lin Zhong, Niraj K. Jha: Towards a Responsive, Yet Power-ef.cient, Operating System: A Holistic Approach. MASCOTS 2005: 249-257 |
| 205 | | Lin Zhong, Niraj K. Jha: Energy efficiency of handheld computer interfaces: limits, characterization and practice. MobiSys 2005: 247-260 |
| 204 | | Lin Zhong, Mike Sinclair, Niraj K. Jha: A personal-area network of low-power wireless interfacing devices for handhelds: system and hardware design. Mobile HCI 2005: 251-254 |
| 203 | | Rui Zhang, Pallav Gupta, Niraj K. Jha: Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies. VLSI Design 2005: 229-234 |
| 202 | | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. VLSI Design 2005: 551-556 |
| 201 | | Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar: Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. VLSI Design 2005: 65-70 |
| 200 | | Loganathan Lingappan, Niraj K. Jha: Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. VTS 2005: 418-423 |
| 199 | | Tat Kee Tan, Anand Raghunathan, Niraj K. Jha: Energy macromodeling of embedded operating systems. ACM Trans. Embedded Comput. Syst. 4(1): 231-254 (2005) |
| 198 | | Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha: Memory binding for performance optimization of control-flow intensive behavioral descriptions. IEEE Trans. VLSI Syst. 13(5): 513-524 (2005) |
| 197 | | Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha: Threshold network synthesis and optimization and its application to nanotechnologies. IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 107-118 (2005) |
| 196 | | Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: Input space-adaptive optimization for embedded-software synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1677-1693 (2005) |
| 195 | | Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Generation of distributed logic-memory architectures through high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1694-1711 (2005) |
| 194 | | Lin Zhong, Niraj K. Jha: Interconnect-aware low-power high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 336-351 (2005) |
| 193 | | Le Yan, Jiong Luo, Niraj K. Jha: Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1030-1041 (2005) |
| 192 | | Yunsi Fei, Niraj K. Jha: Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip. IJES 1(1/2): 2-13 (2005) |
| 2004 | ||
| 191 |  | Laurence Tianruo Yang, Minyi Guo, Guang R. Gao, Niraj K. Jha: Embedded and Ubiquitous Computing, International Conference EUC 2004, Aizu-Wakamatsu City, Japan, August 25-27, 2004, Proceedings Springer 2004 |
| 190 | | Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Automated energy/performance macromodeling of embedded software. DAC 2004: 99-102 |
| 189 | | Abhinav Agrawal, Niraj K. Jha: Synthesis of Reversible Logic. DATE 2004: 1384-1385 |
| 188 | | Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha: Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies. DATE 2004: 904-909 |
| 187 | | Pallav Gupta, Niraj K. Jha: An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology. DATE 2004: 974-979 |
| 186 | | Keith S. Vallerio, Niraj K. Jha: Language Selection for Mobile Systems: Java, C, or Both? ESA/VLSI 2004: 185-191 |
| 185 | | Tat Kee Tan, Anand Raghunathan, Niraj K. Jha: An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded Software. ESA/VLSI 2004: 601-605 |
| 184 | | Keith S. Vallerio, Niraj K. Jha: Evaluating Conditional Statements in Embedded System Software: Systematic Methodologies for Reducing Energy Consumption. ESA/VLSI 2004: 63-69 |
| 183 | | Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Power estimation for cycle-accurate functional descriptions of hardware. ICCAD 2004: 668-675 |
| 182 | | Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: High-level synthesis using computation-unit integrated memories. ICCAD 2004: 783-790 |
| 181 | | Pallav Gupta, Rui Zhang, Niraj K. Jha: An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks. ICCD 2004: 540-543 |
| 180 | | Keith S. Vallerio, Lin Zhong, Niraj K. Jha: Energy-Efficient Graphical User Interface Design. International Conference on Wireless Networks 2004: 959-962 |
| 179 | | Yunsi Fei, Lin Zhong, Niraj K. Jha: An Energy-Aware Framework for Coordinated Dynamic Software Management in Mobile Computers. MASCOTS 2004: 306-317 |
| 178 | | Li Shang, Li-Shiuan Peh, Amit Kumar, Niraj K. Jha: Thermal Modeling, Characterization and Management of On-Chip Networks. MICRO 2004: 67-78 |
| 177 | | Lin Zhong, Niraj K. Jha: Dynamic Power Optimization of Interactive Systems. VLSI Design 2004: 1041-1047 |
| 176 | | Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. VLSI Design 2004: 261-266 |
| 175 | | Weidong Wang, Anand Raghunathan, Niraj K. Jha: Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization. VLSI Design 2004: 267- |
| 174 | | Li Shang, Robert P. Dick, Niraj K. Jha: DESP: A Distributed Economics-Based Subcontracting Protocol for Computation Distribution in Power-Aware Mobile Ad Hoc Networks. IEEE Trans. Mob. Comput. 3(1): 33-45 (2004) |
| 173 | | Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: Input space adaptive design: a high-level methodology for optimizing energy and performance. IEEE Trans. VLSI Syst. 12(6): 590-602 (2004) |
| 172 | | Robert P. Dick, Niraj K. Jha: COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 2-16 (2004) |
| 171 | | Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey: Common-case computation: a high-level energy and performance optimization technique. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 33-49 (2004) |
| 170 | | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Custom-instruction synthesis for extensible-processor platforms. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 216-228 (2004) |
| 169 | | Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: A hybrid energy-estimation technique for extensible processors. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 652-664 (2004) |
| 168 | | Weidong Wang, Anand Raghunathan, Niraj K. Jha, Sujit Dey: Resource budgeting for Multiprocess High-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1010-1019 (2004) |
| 167 | | Jiong Luo, Lin Zhong, Yunsi Fei, Niraj K. Jha: Register binding-based RTL power management for control-flow intensive designs. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1175-1183 (2004) |
| 2003 | ||
| 166 | | Weidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong, Anand Raghunathan, Niraj K. Jha: A comprehensive high-level synthesis system for control-flow intensive behaviors. ACM Great Lakes Symposium on VLSI 2003: 11-14 |
| 165 | | Lin Zhong, Niraj K. Jha: Graphical user interface energy characterization for handheld computers. CASES 2003: 232-242 |
| 164 | | Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Energy Estimation for Extensible Processors. DATE 2003: 10682-10687 |
| 163 | | Tat Kee Tan, Anand Raghunathan, Niraj K. Jha: Software Architectural Transformations: A New Approach to Low Energy Embedded Software. DATE 2003: 11046-11051 |
| 162 | | Jiong Luo, Li-Shiuan Peh, Niraj K. Jha: Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. DATE 2003: 11150-11151 |
| 161 | | Li Shang, Li-Shiuan Peh, Niraj K. Jha: Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. HPCA 2003: 91-102 |
| 160 | | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: A Scalable Application-Specific Processor Synthesis Methodology. ICCAD 2003: 283-290 |
| 159 | | Le Yan, Jiong Luo, Niraj K. Jha: Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems. ICCAD 2003: 30-38 |
| 158 | | Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. ICCAD 2003: 46-53 |
| 157 | | Pallav Gupta, Lin Zhong, Niraj K. Jha: A High-level Interconnect Power Model for Design Space Exploration. ICCAD 2003: 551-559 |
| 156 | | Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha: Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. ICCD 2003: 187-193 |
| 155 | | Li Shang, Li-Shiuan Peh, Niraj K. Jha: PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks. ICS 2003: 98-108 |
| 154 | | Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Analyzing the energy consumption of security protocols. ISLPED 2003: 30-35 |
| 153 | | Jiong Luo, Niraj K. Jha: Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems. VLSI Design 2003: 369-375 |
| 152 | | Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey: High-level Synthesis of Multi-process Behavioral Descriptions. VLSI Design 2003: 467-473 |
| 151 | | Keith S. Vallerio, Niraj K. Jha: Task Graph Extraction for Embedded System Synthesis. VLSI Design 2003: 480- |
| 150 | | Anand Raghunathan, Sujit Dey, Niraj K. Jha: High-level macro-modeling and estimation techniques for switching activity and power consumption. IEEE Trans. VLSI Syst. 11(4): 538-557 (2003) |
| 149 | | Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Analysis of power dissipation in embedded systems using real-time operating systems. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 615-627 (2003) |
| 148 | | Tat Kee Tan, Anand Raghunathan, Niraj K. Jha: A simulation framework for energy-consumption analysis of OS-driven embedded applications. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1284-1294 (2003) |
| 2002 | ||
| 147 | | Jiong Luo, Niraj K. Jha: Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis. HiPC 2002: 679-692 |
| 146 | | Li Shang, Robert P. Dick, Niraj K. Jha: An Economics-based Power-aware Protocol for Computation Distribution in Mobile Ad-Hoc Networks. IASTED PDCS 2002: 339-344 |
| 145 | | Lin Zhong, Niraj K. Jha: Interconnect-aware high-level synthesis for low power. ICCAD 2002: 110-117 |
| 144 | | Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: High-level synthesis of distributed logic-memory architectures. ICCAD 2002: 564-571 |
| 143 | | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Synthesis of custom processors based on extensible platforms. ICCAD 2002: 641-648 |
| 142 | | Lin Zhong, Jiong Luo, Yunsi Fei, Niraj K. Jha: Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors. ICCD 2002: 391-394 |
| 141 | | Tat Kee Tan, Anand Raghunathan, Niraj K. Jha: Embedded Operating System Energy Analysis and Macro-Modeling. ICCD 2002: 515-520 |
| 140 | | Keith S. Vallerio, Niraj K. Jha: Task graph transformation to aid system synthesis. ISCAS (4) 2002: 695-698 |
| 139 | | Yunsi Fei, Niraj K. Jha: Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip. VLSI Design 2002: 274-281 |
| 138 | | Li Shang, Niraj K. Jha: Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs. VLSI Design 2002: 345- |
| 137 | | Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: Input Space Adaptive Embedded Software Synthesis. VLSI Design 2002: 711-718 |
| 136 | | Jiong Luo, Niraj K. Jha: Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. VLSI Design 2002: 719- |
| 135 | | Li Shang, Li-Shiuan Peh, Niraj K. Jha: Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links. Computer Architecture Letters 1: (2002) |
| 134 | | Kamal S. Khouri, Niraj K. Jha: Leakage power analysis and reduction during behavioral synthesis. IEEE Trans. VLSI Syst. 10(6): 876-885 (2002) |
| 133 | | Srivaths Ravi, Niraj K. Jha: Test synthesis of systems-on-a-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1211-1217 (2002) |
| 132 | | Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: High-level test compaction techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 827-841 (2002) |
| 131 | | Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: High-level energy macromodeling of embedded software. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1037-1050 (2002) |
| 2001 | ||
| 130 | | Jiong Luo, Niraj K. Jha: Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems. DAC 2001: 444-449 |
| 129 | | Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: High-level Software Energy Macro-modeling. DAC 2001: 605-610 |
| 128 | | Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. DAC 2001: 738-743 |
| 127 | | Niraj K. Jha: Low Power System Scheduling and Synthesis. ICCAD 2001: 259-263 |
| 126 | | Li Shang, Niraj K. Jha: High-Level Power Modeling of CPLDs and FPGAs. ICCD 2001: 46-53 |
| 125 | | Srivaths Ravi, Niraj K. Jha: Fast test generation for circuits with RTL and gate-level views. ITC 2001: 1068-1077 |
| 124 | | Srivaths Ravi, Niraj K. Jha: Synthesis of System-on-a-chip for Testability. VLSI Design 2001: 149-156 |
| 123 | | Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: TAO: regular expression-based register-transfer level testability analysis and optimization. IEEE Trans. VLSI Syst. 9(6): 824-832 (2001) |
| 122 | | Kamal S. Khouri, Niraj K. Jha: Clock selection for performance optimization of control-flowintensive behaviors. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 158-165 (2001) |
| 121 | | Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha: Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. IEEE Trans. on CAD of Integrated Circuits and Systems 20(12): 1414-1425 (2001) |
| 120 | | Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: Testing of core-based systems-on-a-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 426-439 (2001) |
| 2000 | ||
| 119 | | Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Power analysis of embedded operating systems. DAC 2000: 312-315 |
| 118 | | Jiong Luo, Niraj K. Jha: Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems. ICCAD 2000: 357-364 |
| 117 | | Kamal S. Khouri, Niraj K. Jha: Leakage Power Analysis and Reduction during Behavioral Synthesis. ICCD 2000: 561-564 |
| 116 | | Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana: A Technique for Identifying RTL and Gate-Level Correspondences. ICCD 2000: 591- |
| 115 | | Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: : Reducing test application time in high-level test generation. ITC 2000: 829-838 |
| 114 | | Robert P. Dick, Niraj K. Jha: COWLS: Hardware-Software Co-Synthesis of Distributed Wireless Low-Power Embedded Client-Server Systems. VLSI Design 2000: 114- |
| 113 | | Kamal S. Khouri, Niraj K. Jha: Clock Selection for Performance Optimization of Control-Flow Intensive Behaviors. VLSI Design 2000: 523-529 |
| 112 | | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis. IEEE Trans. Computers 49(9): 865-885 (2000) |
| 111 | | Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik: A BIST scheme for RTL circuits based on symbolic testabilityanalysis. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 111-128 (2000) |
| 110 | | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs. IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 308-324 (2000) |
| 109 | | Indradeep Ghosh, Sujit Dey, Niraj K. Jha: A fast and low-cost testing technique for core-based system-chips. IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 863-877 (2000) |
| 108 | | Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 894-906 (2000) |
| 1999 | ||
| 107 | | Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey: Common-Case Computation: A High-Level Technique for Power and Performance Optimization. DAC 1999: 56-61 |
| 106 | | Robert P. Dick, Niraj K. Jha: MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis. DATE 1999: 263-270 |
| 105 | | Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: A framework for testing core-based systems-on-a-chip. ICCAD 1999: 385-390 |
| 104 | | Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha: Memory binding for performance optimization of control-flow intensive behaviors. ICCAD 1999: 482-488 |
| 103 | | Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. VTS 1999: 398-406 |
| 102 | | Bharat P. Dave, Niraj K. Jha: COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded Systems. IEEE Trans. Computers 48(4): 417-441 (1999) |
| 101 | | S. Srinivasan, Niraj K. Jha: Safety and Reliability Driven Task Allocation in Distributed Systems. IEEE Trans. Parallel Distrib. Syst. 10(3): 238-251 (1999) |
| 100 | | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey: Power management in high-level synthesis. IEEE Trans. VLSI Syst. 7(1): 7-15 (1999) |
| 99 | | Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha: COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems. IEEE Trans. VLSI Syst. 7(1): 92-104 (1999) |
| 98 | | Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi: Controller-based power management for control-flow intensive designs. IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1496-1508 (1999) |
| 97 | | Robert P. Dick, Niraj K. Jha: Corrections to "mogac: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems". IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1527-1527 (1999) |
| 96 | | Ganesh Lakshminarayana, Niraj K. Jha: FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1577-1594 (1999) |
| 95 | | Indradeep Ghosh, Niraj K. Jha, Sujit Dey: A low overhead design for testability and test generation technique for core-based systems-on-a-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1661-1676 (1999) |
| 94 | | Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha: High-level synthesis of low-power control-flow intensive circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1715-1729 (1999) |
| 93 | | Ganesh Lakshminarayana, Niraj K. Jha: High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 265-281 (1999) |
| 92 | | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha: Hierarchical test generation and design for testability methods for ASPPs and ASIPs. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 357-370 (1999) |
| 91 | | Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha: Wavesched: a novel scheduling technique for control-flow intensive designs. IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 505-523 (1999) |
| 90 | | Anand Raghunathan, Sujit Dey, Niraj K. Jha: Register transfer level power optimization with emphasis on glitch analysis and reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 18(8): 1114-1131 (1999) |
| 1998 | ||
| 89 | | Ganesh Lakshminarayana, Niraj K. Jha: FACT: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions. DAC 1998: 102-107 |
| 88 | | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. DAC 1998: 108-113 |
| 87 | | Ganesh Lakshminarayana, Niraj K. Jha: Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions. DAC 1998: 439-444 |
| 86 | | Indradeep Ghosh, Sujit Dey, Niraj K. Jha: A Fast and Low Cost Testing Technique for Core-Based System-on-Chip. DAC 1998: 542-547 |
| 85 | | Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik: A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. DAC 1998: 554-559 |
| 84 | | Bharat P. Dave, Niraj K. Jha: CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures. DATE 1998: 118-124 |
| 83 | | Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha: IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits. DATE 1998: 848-854 |
| 82 | | Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. ICCAD 1998: 577-584 |
| 81 | | Robert P. Dick, Niraj K. Jha: CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems. ICCAD 1998: 62-67 |
| 80 | | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey: Transforming control-flow intensive designs to facilitate power management. ICCAD 1998: 657-664 |
| 79 | | Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha: Fast high-level power estimation for control-flow intensive design. ISLPED 1998: 299-304 |
| 78 | | Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: TAO: regular expression based high-level testability analysis and optimization. ITC 1998: 331-340 |
| 77 | | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey: A Power Management Methodology for High-Level Synthesis. VLSI Design 1998: 24-19 |
| 76 | | Bharat P. Dave, Niraj K. Jha: COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System Architectures. VLSI Design 1998: 347-354 |
| 75 | | Sandeep Bhatia, Niraj K. Jha: Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits. IEEE Trans. VLSI Syst. 6(4): 608-619 (1998) |
| 74 | | Bharat P. Dave, Niraj K. Jha: COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 900-919 (1998) |
| 73 | | Robert P. Dick, Niraj K. Jha: MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 920-935 (1998) |
| 72 | | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha: A design-for-testability technique for register-transfer level circuits using control/data flow extraction. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 706-723 (1998) |
| 71 | | Indradeep Ghosh, Niraj K. Jha: High-level test synthesis: a survey. Integration 26(1-2): 79-99 (1998) |
| 70 | | Niraj K. Jha: Guest Editorial. J. Electronic Testing 13(2): 77 (1998) |
| 1997 | ||
| 69 | | Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi: Power Management Techniques for Control-Flow Intensive Designs. DAC 1997: 429-434 |
| 68 | | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha: Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. DAC 1997: 534-539 |
| 67 | | Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha: COSYN: Hardware-Software Co-Synthesis of Embedded Systems. DAC 1997: 703-708 |
| 66 | | Bharat P. Dave, Niraj K. Jha: COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded System Architectures for Low Overhead Fault Tolerance. FTCS 1997: 339-348 |
| 65 | | Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha: Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions. ICCAD 1997: 244-250 |
| 64 | | Robert P. Dick, Niraj K. Jha: MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems. ICCAD 1997: 522-529 |
| 63 | | Indradeep Ghosh, Niraj K. Jha, Sujit Dey: A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems. ITC 1997: 50-59 |
| 62 | | Shalini Yajnik, Niraj K. Jha: Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems. IEEE Trans. Parallel Distrib. Syst. 8(2): 137-153 (1997) |
| 61 | | Shalini Yajnik, Niraj K. Jha: Analysis and Randomized Design of Algorithm-Based Fault Tolerant Multiprocessor Systems Under an Extended Model. IEEE Trans. Parallel Distrib. Syst. 8(7): 757-768 (1997) |
| 60 | | Anand Raghunathan, Niraj K. Jha: SCALP: an iterative-improvement-based low-power data path synthesis system. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1260-1277 (1997) |
| 59 | | Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng: Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. IEEE Trans. on CAD of Integrated Circuits and Systems 16(12): 1514-1521 (1997) |
| 58 | | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha: Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 1001-1014 (1997) |
| 1996 | ||
| 57 | | Anand Raghunathan, Sujit Dey, Niraj K. Jha: Glitch Analysis and Reduction in Register Transfer Level. DAC 1996: 331-336 |
| 56 | | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis. FTCS 1996: 336-345 |
| 55 | | Anand Raghunathan, Sujit Dey, Niraj K. Jha: Register-transfer level estimation techniques for switching activity and power consumption. ICCAD 1996: 158-165 |
| 54 | | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha: A design for testability technique for RTL circuits using control/data flow extraction. ICCAD 1996: 329-336 |
| 53 | | Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi: Controller re-specification to minimize switching activity in controller/data path circuits. ISLPED 1996: 301-304 |
| 52 | | J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard: Hardware-Software Co-Design for Test: It's the Last Straw! VTS 1996: 506-507 |
| 51 | | Sandeep Bhatia, Niraj K. Jha: Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. IEEE Trans. on CAD of Integrated Circuits and Systems 15(2): 228-243 (1996) |
| 1995 | ||
| 50 | | Santhanam Srinivasan, Niraj K. Jha: Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems. EURO-DAC 1995: 334-339 |
| 49 | | Anand Raghunathan, Niraj K. Jha: An iterative improvement algorithm for low power data path synthesis. ICCAD 1995: 597-602 |
| 48 | | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha: Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. ICCD 1995: 173-179 |
| 47 | | Santhanam Srinivasan, Niraj K. Jha: Task Allocation for Safety and Reliability in Distributed Systems. ICPP (2) 1995: 206-213 |
| 46 | | Anand Raghunathan, Niraj K. Jha: An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation. ISCAS 1995: 1069-1073 |
| 45 | | Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng: Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. VLSI Design 1995: 171-176 |
| 1994 | ||
| 44 | | Sandeep Bhatia, Niraj K. Jha: Genesis: A Behavioral Synthesis System for Hierarchical Testability. EDAC-ETC-EUROASIC 1994: 272-276 |
| 43 | | Anand Raghunathan, Niraj K. Jha: Behavioral Synthesis for low Power. ICCD 1994: 318-322 |
| 42 | | Sandeep Bhatia, Niraj K. Jha: Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches. ICCD 1994: 91-96 |
| 41 | | Shalini Yajnik, Niraj K. Jha: Synthesis of Fault Tolerant Architectures for Molecular Dynamics. ISCAS 1994: 247-250 |
| 40 | | Shalini Yajnik, Niraj K. Jha: Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems. ISCAS 1994: 333-336 |
| 39 | | Steven W. Burns, Niraj K. Jha: A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme. IEEE Trans. Computers 43(4): 490-495 (1994) |
| 38 | | Sying-Jyan Wang, Niraj K. Jha: Algorithm-Based Fault Tolerance for FFT Networks. IEEE Trans. Computers 43(7): 849-854 (1994) |
| 37 | | Bapiraju Vinnakota, Niraj K. Jha: Design of Algorithm-Based Fault-Tolerant Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. IEEE Trans. Parallel Distrib. Syst. 5(10): 1099-1106 (1994) |
| 36 | | Jennifer Rexford, Niraj K. Jha: Partitioned Encoding Schemes for Algorithm-Based Fault Tolerance in Massively Parallel Systems. IEEE Trans. Parallel Distrib. Syst. 5(6): 649-653 (1994) |
| 1993 | ||
| 35 | | Tien-Chien Lee, Niraj K. Jha, Wayne Wolf: Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments. DAC 1993: 292-297 |
| 34 | | Sandeep Bhatia, Niraj K. Jha: Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan. ICCD 1993: 151-154 |
| 33 | | Santhanam Srinivasan, Niraj K. Jha: Efficient Diagnosis in Algorithm-Based Fault Tolerant Multiprocessor Systems. ICCD 1993: 592-595 |
| 32 | | Shalini Yajnik, Niraj K. Jha: Design of Algorithm-Based Fault Tolerant Systems With In-System Checks. ICPP 1993: 246-253 |
| 31 | | Tien-Chien Lee, Niraj K. Jha, Wayne Wolf: A Conditional Resource-Sharing Method for Behavior Synthesis of Highly- Testable Data Paths. ITC 1993: 744-753 |
| 30 | | Sandeep Bhatia, Niraj K. Jha: Synthesis of Sequential Circuits for Robust Path Delay Fault Testability. VLSI Design 1993: 275-280 |
| 29 | | Niraj K. Jha: Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers. IEEE Trans. Computers 42(2): 179-189 (1993) |
| 28 | | Ramesh K. Sitaraman, Niraj K. Jha: Optimal Design of Checks for Error Detection and Location in Fault-Tolerant Multiprocessor Systems. IEEE Trans. Computers 42(7): 780-793 (1993) |
| 27 | | Bapiraju Vinnakota, Niraj K. Jha: Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems. IEEE Trans. Computers 42(8): 924-937 (1993) |
| 26 | | Bapiraju Vinnakota, Niraj K. Jha: Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs. IEEE Trans. Parallel Distrib. Syst. 4(8): 864-874 (1993) |
| 25 | | Niraj K. Jha, Abha Ahuja: Easily testable nonrestoring and restoring gate-level cellular array dividers. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 114-123 (1993) |
| 24 | | Niraj K. Jha, Sying-Jyan Wang: Design and synthesis of self-checking VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(6): 878-887 (1993) |
| 1992 | ||
| 23 | | Niraj K. Jha, Irith Pomeranz, Sudhakar M. Reddy, Robert J. Miller: Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability. FTCS 1992: 280-287 |
| 22 | | Tien-Chien Lee, Wayne Wolf, Niraj K. Jha: Behavioral synthesis for easy testability in data path scheduling. ICCAD 1992: 616-619 |
| 21 | | Tien-Chien Lee, Wayne Wolf, Niraj K. Jha, John M. Acken: Behavioral Synthesis for Easy Testability in Data Path Allocation. ICCD 1992: 29-32 |
| 20 | | Niraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka: Multiple Input Bridging Fault Detection in CMOS Sequential Circuits. ICCD 1992: 369-372 |
| 19 | | Shalini Yajnik, Niraj K. Jha: Design and Analysis of Fault-Detecting and Fault-Locating Schedules for Computation DAGs. IPPS 1992: 348-351 |
| 1991 | ||
| 18 | | Bapiraju Vinnakota, Niraj K. Jha: Design of Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. FTCS 1991: 504-511 |
| 17 | | Ramesh K. Sitaraman, Niraj K. Jha: Optimal Design of Checks for Error Detection and Location in Fault Tolerant Multiprocessors Systems. Fault-Tolerant Computing Systems 1991: 396-406 |
| 16 | | Niraj K. Jha, Sying-Jyan Wang: Design and Synthesis of Self-Checking VLSI Circuits and Systems. ICCD 1991: 578-581 |
| 15 | | Niraj K. Jha: Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codes. IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 136-143 (1991) |
| 14 | | Konstantinos I. Diamantaras, Niraj K. Jha: A new transition count method for testing of logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(3): 407-410 (1991) |
| 13 | | Andres R. Takach, Niraj K. Jha: Easily testable gate-level and DCVS multipliers. IEEE Trans. on CAD of Integrated Circuits and Systems 10(7): 932-942 (1991) |
| 12 | | Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha: Design of robustly testable combinational logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 1036-1048 (1991) |
| 1990 | ||
| 11 | | Niraj K. Jha, Qiao Tong: Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring. EURO-DAC 1990: 350-354 |
| 10 | | Bapiraju Vinnakota, Niraj K. Jha: A dependence graph-based approach to the design of algorithm-based fault tolerant systems. FTCS 1990: 122-129 |
| 9 | | Niraj K. Jha: Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 9(3): 332-336 (1990) |
| 1989 | ||
| 8 | | Niraj K. Jha: Fault detection in CVS parity trees: application in SSC CVS parity and two-rail checkers. FTCS 1989: 407-414 |
| 7 | | Niraj K. Jha: Separable codes for detecting unidirectional errors. IEEE Trans. on CAD of Integrated Circuits and Systems 8(5): 571-574 (1989) |
| 6 | | Niraj K. Jha: A totally self-checking checker for Borden's code. IEEE Trans. on CAD of Integrated Circuits and Systems 8(7): 731-736 (1989) |
| 1988 | ||
| 5 | | Niraj K. Jha: Multiple Stuck-Open Fault Detection in CMOS Logic Circuits. IEEE Trans. Computers 37(4): 426-432 (1988) |
| 4 | | Niraj K. Jha: Testing for multiple faults in domino-CMOS logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 7(1): 109-116 (1988) |
| 3 | | Gopal Gupta, Niraj K. Jha: A universal test set for CMOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 7(5): 590-597 (1988) |
| 1986 | ||
| 2 | | Niraj K. Jha: Detecting Multiple Faults in CMOS Circuits. ITC 1986: 514-519 |
| 1985 | ||
| 1 | | Niraj K. Jha, Jacob A. Abraham: Design of Testable CMOS Logic Circuits Under Arbitrary Delays. IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 264-269 (1985) |
Colors in the list of coauthors
Last update Fri Jun 1 15:44:53 2012 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page