Rakesh Gnana David Jeyasingh

	2011
2		Rakesh Gnana David Jeyasingh, Navakanta Bhat, Bharadwaj S. Amrutur: Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique. IEEE Trans. VLSI Syst. 19(2): 295-304 (2011)
	2008
1		Rakesh Gnana David Jeyasingh, Navakanta Bhat: A low power, process invariant keeper for high speed dynamic logic circuits. ISCAS 2008: 1668-1671

Coauthor Index

1	Bharadwaj S. Amrutur (Bharadwaj Amrutur)	[2]
2	Navakanta Bhat	[1] [2]

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