 | 2012 |
|---|
| 11 |       | Maximilian Mittag,
Andreas Krinke,
Göran Jerke,
Wolfgang Rosenstiel:
Hierarchical propagation of geometric constraints for full-custom physical design of ICs.
DATE 2012: 1471-1474 |
| 2010 |
|---|
| 10 | | Göran Jerke,
Jens Lienig:
Early-stage determination of current-density criticality in interconnects.
ISQED 2010: 667-674 |
| 2009 |
|---|
| 9 | | Ammar Nassaj,
Jens Lienig,
Goeran Jerke:
A new methodology for constraint-driven layout design of analog circuits.
ICECS 2009: 996-999 |
| 8 | | Göran Jerke,
Jens Lienig:
Constraint-driven design: the next step towards analog design automation.
ISPD 2009: 75-82 |
| 2008 |
|---|
| 7 | | Jan B. Freuer,
Göran Jerke,
Joachim Gerlach,
Wolfgang Nebel:
On the Verification of High-Order Constraint Compliance in IC Design.
DATE 2008: 26-31 |
| 2005 |
|---|
| 6 | | Jens Lienig,
Göran Jerke:
Electromigration-Aware Physical Design of Integrated Circuits.
VLSI Design 2005: 77-82 |
| 2004 |
|---|
| 5 | | Goeran Jerke,
Jens Lienig,
Jürgen Scheible:
Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs.
DAC 2004: 181-184 |
| 4 | | Göran Jerke,
Jens Lienig:
Hierarchical current-density verification in arbitrarily shaped metallization patterns of analog circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 80-90 (2004) |
| 2002 |
|---|
| 3 | | Goeran Jerke,
Jens Lienig:
Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog Circuits.
DATE 2002: 464-469 |
| 2 | | Jens Lienig,
Goeran Jerke,
Thorsten Adler:
Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing.
VLSI Design 2002: 372- |
| 2001 |
|---|
| 1 | | Jens Lienig,
Goeran Jerke,
Thorsten Adler:
AnalogRouter: a new approach of current-driven routing for analog circuits.
DATE 2001: 819 |
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