Maksim Jenihhin

	2011
15		Taavi Viilukas, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Samary Baranov: Automated test bench generation for high-level synthesis flow ABELITE. EWDTS 2011: 13-16
14		Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara: Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. European Test Symposium 2011: 147-152
	2010
13		Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko: Constraint-based test pattern generation at the Register-Transfer Level. DDECS 2010: 352-357
12		Maksim Jenihhin, Jaan Raik, Raimund Ubar, Tatjana Shchenova: An approach for PSL assertion coverage analysis with high-level decision diagrams. EWDTS 2010: 13-16
	2009
11		Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar: PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams. J. Electronic Testing 25(6): 289-300 (2009)
	2008
10		Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee: Code Coverage Analysis using High-Level Decision Diagrams. DDECS 2008: 201-206
9		Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee: Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. DELTA 2008: 222-227
8		Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz: Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. DSD 2008: 729-734
7		Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar: Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation. European Test Symposium 2008: 61-68
6		Jaan Raik, Raimund Ubar, Taavi Viilukas, Maksim Jenihhin: Mixed hierarchical-functional fault models for targeting sequential cores. Journal of Systems Architecture - Embedded Systems Design 54(3-4): 465-477 (2008)
	2007
5		Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski: Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS 2007: 35-40
	2006
4		Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin: Test Time Minimization for Hybrid BIST of Core-Based Systems. J. Comput. Sci. Technol. 21(6): 907-912 (2006)
	2004
3		Raimund Ubar, Maksim Jenihhin: Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting. DELTA 2004: 3-8
	2003
2		Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin: Test Time Minimization for Hybrid BIST of Core-Based Systems. Asian Test Symposium 2003: 318-325
1		Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin: Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. DFT 2003: 225-

Coauthor Index

1	Samary Baranov	[15]
2	Anton Chepurov	[7] [11]
3	Sergei Devadze	[9]
4	Petru Eles	[1] [2] [4]
5	Peeter Ellervee	[9] [10]
6	Hideo Fujiwara	[14]
7	Gert Jervan	[1] [2] [4] [9]
8	Anna Krivenko	[13]
9	Wieslaw Kuzmicz	[8]
10	Zebo Peng	[1] [2] [4]
11	Witold A. Pleskacz	[5] [8]
12	Jaan Raik	[5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
13	Michal Rakowski	[5] [8]
14	Anna Rannaste	[14]
15	Uljana Reinsalu	[10]
16	Tatjana Shchenova	[12]
17	Raimund Ubar	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
18	Taavi Viilukas	[6] [13] [14] [15]

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