Sunghyun Jee

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2002

4 Sunghyun Jee, Kannappan Palaniappan: Compiler Processor Tradeoffs for DISVLIW Architecture. ISPAN 2002: 199-204

3 Sunghyun Jee, Kannappan Palaniappan: Dynamically Scheduling VLIW Instructions with Dependency Information. Interaction between Compilers and Computer Architectures 2002: 15-23

2 Sunghyun Jee, Kannappan Palaniappan: Performance evaluation for a compressed-VLIW processor. SAC 2002: 913-917

2001

1 Sunghyun Jee, Sukil Kim: A Design of A Processor Architecture for Codes With Explicit Data Dependencies. PPSC 2001

	2002
4		Sunghyun Jee, Kannappan Palaniappan: Compiler Processor Tradeoffs for DISVLIW Architecture. ISPAN 2002: 199-204
3		Sunghyun Jee, Kannappan Palaniappan: Dynamically Scheduling VLIW Instructions with Dependency Information. Interaction between Compilers and Computer Architectures 2002: 15-23
2		Sunghyun Jee, Kannappan Palaniappan: Performance evaluation for a compressed-VLIW processor. SAC 2002: 913-917
	2001
1		Sunghyun Jee, Sukil Kim: A Design of A Processor Architecture for Codes With Explicit Data Dependencies. PPSC 2001

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