Abhijit Jas

	2011
31		Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris: AVF Analysis Acceleration via Hierarchical Fault Pruning. European Test Symposium 2011: 87-92
30		Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris: Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller. IEEE Trans. Computers 60(9): 1260-1273 (2011)
29		Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Chandra Tirumurti, Yiorgos Makris: Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor. IEEE Trans. Computers 60(9): 1274-1287 (2011)
	2010
28		Daniele Rossi, Martin Omaña, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche: Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. Conf. Computing Frontiers 2010: 113-114
27		Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou: Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 466-478 (2010)
	2009
26		Naghmeh Karimi, Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris: Impact analysis of performance faults in modern microprocessors. ICCD 2009: 91-96
25		Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti: RT-Level Deviation-Based Grading of Functional Test Sequences. VTS 2009: 264-269
24		Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris: Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller. VTS 2009: 9-14
23		Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas: FPGA-based hardware acceleration for Boolean satisfiability. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009)
	2008
22		Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou: Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. ASP-DAC 2008: 486-491
21		Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche: A low-cost concurrent error detection technique for processor control logic. DATE 2008: 897-902
20		Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris, Abhijit Jas, Chandra Tirumurti: Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller. DFT 2008: 454-462
19		Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche: Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic. European Test Symposium 2008: 171-176
18		Avijit Dutta, Abhijit Jas: Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes. ISQED 2008: 68-73
17		Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Yiorgos Makris: On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors. ITC 2008: 1-10
16		Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty: A Methodology for Handling Complex Functional Constraints for Large Industrial Designs. J. Electronic Testing 24(1-3): 259-269 (2008)
	2007
15		Abhijit Jas, Srinivas Patil: Analysis of Specified Bit Handling Capability of Combinational Expander Networks. DFT 2007: 252-260
	2006
14		Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty: An Approach to Minimizing Functional Constraints. DFT 2006: 215-226
	2004
13		C. V. Krishna, Abhijit Jas, Nur A. Touba: Achieving high encoding efficiency with partial dynamic LFSR reseeding. ACM Trans. Design Autom. Electr. Syst. 9(4): 500-516 (2004)
12		Abhijit Jas, C. V. Krishna, Nur A. Touba: Weighted pseudorandom hybrid BIST. IEEE Trans. VLSI Syst. 12(12): 1277-1283 (2004)
11		Abhijit Jas, Bahram Pouya, Nur A. Touba: Test data compression technique for embedded cores using virtual scan chains. IEEE Trans. VLSI Syst. 12(7): 775-781 (2004)
	2003
10		Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba: An efficient test vector compression scheme using selective Huffman coding. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 797-806 (2003)
	2002
9		Abhijit Jas, Nur A. Touba: Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor. J. Electronic Testing 18(4-5): 503-514 (2002)
	2001
8		C. V. Krishna, Abhijit Jas, Nur A. Touba: Test vector encoding using partial LFSR reseeding. ITC 2001: 885-893
7		Abhijit Jas, C. V. Krishna, Nur A. Touba: Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme. VTS 2001: 2-8
	2000
6		Abhijit Jas, Bahram Pouya, Nur A. Touba: Virtual Scan Chains: A Means for Reducing Scan Length in Cores. VTS 2000: 73-78
	1999
5		Abhijit Jas, Kartik Mohanram, Nur A. Touba: An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. Asian Test Symposium 1999: 275-
4		Abhijit Jas, Nur A. Touba: Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. ICCD 1999: 418-
3		W. Quddus, Abhijit Jas, Nur A. Touba: Configuration self-test in FPGA-based reconfigurable systems. ISCAS (1) 1999: 97-100
2		Abhijit Jas, Jayabrata Ghosh-Dastidar, Nur A. Touba: Scan Vector Compression/Decompression Using Statistical Coding. VTS 1999: 114-120
	1998
1		Abhijit Jas, Nur A. Touba: Test vector decompression via cyclical scan chains and its application to testing core-based designs. ITC 1998: 458-464

Coauthor Index

1	Jacob A. Abraham	[21]
2	Gianluca Berghella	[28]
3	Krishnendu Chakrabarty	[25]
4	Sreejit Chakravarty	[14] [16]
5	Yi-Shing Chang	[14] [16]
6	Debasish Das	[22] [27]
7	Avijit Dutta	[18]
8	Hongxia Fang	[25]
9	Rajesh Galivanche	[19] [21] [28]
10	Jayabrata Ghosh-Dastidar	[2] [10]
11	Kanupriya Gulati	[23]
12	Naghmeh Karimi	[17] [20] [24] [26] [29] [30]
13	Chandramouli V. Kashyap	[22] [27]
14	Sunil P. Khatri	[23]
15	Kip Killpack	[22] [27]
16	C. V. Krishna	[7] [8] [12] [13]
17	Yiorgos Makris	[17] [20] [24] [26] [29] [30] [31]
18	Michail Maniatakos	[17] [20] [24] [26] [29] [30] [31]
19	Cecilia Metra	[19] [28]
20	Kartik Mohanram	[5]
21	Mom-Eng Ng	[10]
22	Martin Omaña	[19] [28]
23	Srinivas Patil	[15] [21] [23] [25]
24	Suganth Paul	[23]
25	Bahram Pouya	[6] [11]
26	W. Quddus	[3]
27	Daniele Rossi	[19] [28]
28	Chandra Tirumurti	[20] [24] [25] [26] [28] [29] [30] [31]
29	Nur A. Touba	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
30	Ramtilak Vemu	[21]
31	Hai Zhou	[22] [27]

Colors in the list of coauthors

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