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Najmi T. Jarwala Coauthor index pubzone.org

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12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNajmi T. Jarwala: Designing "Dual Personality" IEEE 1149.1 Compliant Multi-Chip Modules. J. Electronic Testing 10(1-2): 77-86 (1997)
1996
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNajmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau: Lessons Learned from Practical Applications of BIST/B-S Technology. Asian Test Symposium 1996: 251-257
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJ. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard: Hardware-Software Co-Design for Test: It's the Last Straw! VTS 1996: 506-507
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLBernd Könemann, Ben Bennetts, Najmi T. Jarwala, Benoit Nadeau-Dostie: Built-In Self-Test: Assuring System Integrity. IEEE Computer 29(11): 39-45 (1996)
1995
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLWuudiann Ke, Duy Le, Najmi T. Jarwala: A Secure Data Transmission Scheme for 1149.1 Backplane Test Bus. ITC 1995: 789-796
1994
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNajmi T. Jarwala: Designing "Dual-Personality" IEEE 1149.1-Compliant Multi-Chip Modules. ITC 1994: 446-455
1992
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNajmi T. Jarwala, Paul Stiling, Enn Tammaru, Chi W. Yau: A Framework for Boundary-Scan Based System Test Diagnosis. ITC 1992: 993-998
1991
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNajmi T. Jarwala, Chi W. Yau: Achieving Board-Level BIST Using the Boundary-Scan Master. ITC 1991: 649-658
1990
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChi W. Yau, Najmi T. Jarwala: The boundary-scan master: target applications and functional requirements. ITC 1990: 311-315
1989
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNajmi T. Jarwala, Chi W. Yau: A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects. ITC 1989: 63-70
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNajmi T. Jarwala, Chi W. Yau: A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects. ITC 1989: 71-77
1988
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNajmi T. Jarwala, Dhiraj K. Pradhan: TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's. IEEE Trans. Computers 37(10): 1235-1250 (1988)

Coauthor Index

1Ben Bennetts (R. G. Bennetts) [9]
2J. El-Ziq [10]
3Niraj K. Jha [10]
4Wuudiann Ke [8]
5Bernd Könemann [9]
6Duy Le [8]
7Peter Marwedel [10]
8Benoit Nadeau-Dostie [9]
9Christos A. Papachristou [10]
10Dhiraj K. Pradhan [1]
11Janusz Rajski [10]
12Paul W. Rutkowski [11]
13John W. Sheppard [10]
14Paul Stiling [6]
15Enn Tammaru [6]
16Shianling Wu [11]
17Chi W. Yau [2] [3] [4] [5] [6] [11]

Colors in the list of coauthors

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