Stephen Jang

	2012
9		Sayak Ray, Alan Mishchenko, Niklas Eén, Robert K. Brayton, Stephen Jang, Chao Chen: Mapping into LUT structures. DATE 2012: 1579-1584
	2011
8		Alan Mishchenko, Robert K. Brayton, Stephen Jang, Victor N. Kravets: Delay optimization using SOP balancing. ICCAD 2011: 375-382
7		Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, Stephen Jang: Scalable don't-care-based logic optimization and resynthesis. TRETS 4(4): 34 (2011)
	2010
6		Alan Mishchenko, Robert K. Brayton, Stephen Jang: Global delay optimization using structural choices. FPGA 2010: 181-184
	2009
5		Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang: Scalable don't-care-based logic optimization and resynthesis. FPGA 2009: 151-160
4		Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton: SmartOpt: an industrial strength framework for logic synthesis. FPGA 2009: 237-240
3		Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko: WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging. TRETS 2(2): (2009)
	2008
2		Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko: WireMap: FPGA technology mapping for improved routability. FPGA 2008: 47-55
1		Alan Mishchenko, Michael L. Case, Robert K. Brayton, Stephen Jang: Scalable and scalably-verifiable sequential synthesis. ICCAD 2008: 234-241

Coauthor Index

1	Robert K. Brayton	[1] [4] [5] [6] [7] [8] [9]
2	Michael L. Case	[1]
3	Billy Chan	[2] [3] [4]
4	Chao Chen	[9]
5	Kevin Chung	[2] [3] [4]
6	Niklas Eén	[9]
7	Mark Jarvin	[4]
8	Jie-Hong Roland Jiang (Jie-Hong R. Jiang)	[5] [7]
9	Victor N. Kravets	[8]
10	Alan Mishchenko	[1] [2] [3] [4] [5] [6] [7] [8] [9]
11	Sayak Ray	[9]
12	Dennis Wu	[4]

Last update Fri Jun 1 15:44:53 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page