Hochang Jang

List of publications from the DBLP Bibliography Server - FAQ

Ask others: ACM DL/Guide -

2011

2 Hochang Jang, Deokjin Joo, Taewhan Kim: Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 30(1): 96-109 (2011)

2009

1 Hochang Jang, Taewhan Kim: Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization. DAC 2009: 794-799

	2011
2		Hochang Jang, Deokjin Joo, Taewhan Kim: Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 30(1): 96-109 (2011)
	2009
1		Hochang Jang, Taewhan Kim: Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization. DAC 2009: 794-799

Coauthor Index

Last update Fri Jun 1 15:44:53 2012 CET by the DBLP Team —

Data released under the ODC-BY 1.0 license — See also our legal information page