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Andhi Janapsatya Coauthor index pubzone.org

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DBLP keys2010
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran: SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. DAC 2010: 356-361
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHaris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran: Rapid runtime estimation methods for pipelined MPSoCs. DATE 2010: 363-368
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran: DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. DATE 2010: 496-501
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAndhi Janapsatya, Aleksandar Ignjatovic, Jorgen Peddersen, Sri Parameswaran: Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. DATE 2010: 920-925
2009
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAndhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic: HitME: low power Hit MEmory buffer for embedded systems. ASP-DAC 2009: 335-340
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran: SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems. CODES+ISSS 2009: 295-304
2007
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAndhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Jörg Henkel: Instruction trace compression for rapid instruction cache simulation. DATE 2007: 803-808
2006
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAndhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran: A novel instruction scratchpad memory optimization method based on concomitance metric. ASP-DAC 2006: 612-617
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAndhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran: Finding optimal L1 cache configuration for embedded systems. ASP-DAC 2006: 796-801
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAndhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran: Exploiting statistical information for implementation of instruction scratchpad memory in embedded system. IEEE Trans. VLSI Syst. 14(8): 816-829 (2006)
2005
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran: Rapid Embedded Hardware/Software System Generation. VLSI Design 2005: 111-116
2004
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAndhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic: Hardware/software managed scratchpad memory for embedded system. ICCAD 2004: 370-377

Coauthor Index

1Mohammad Shihabul Haque [7] [10] [11] [12]
2Jörg Henkel [6]
3Aleksandar Ignjatovic [1] [3] [4] [5] [6] [8] [9]
4Haris Javaid [11]
5Sri Parameswaran [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
6Jorgen Peddersen [2] [9] [10] [12]
7Seng Lin Shee [2]

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