 | 2010 |
|---|
| 10 |       | Jithendra Srinivas,
Sukumar Jairam:
Clock gating approaches by IOEX graphs and cluster efficiency plots.
DATE 2010: 638-641 |
| 2009 |
|---|
| 9 | | Jithendra Srinivas,
Madhusudan Rao,
Sukumar Jairam,
H. Udayakumar,
Jagdish C. Rao:
Clock gating effectiveness metrics: Applications to power optimization.
ISQED 2009: 482-487 |
| 2008 |
|---|
| 8 | | Sukumar Jairam,
Madhusudan Rao,
Jithendra Srinivas,
Parimala Vishwanath,
H. Udayakumar,
Jagdish C. Rao:
Clock gating for power optimization in ASIC design cycle theory & practice.
ISLPED 2008: 307-308 |
| 7 | | Sukumar Jairam,
S. M. Stalin,
Jean-Yves Oberle,
H. Udayakumar:
An SSO Based Methodology for EM Emission Estimation from SoCs.
ISQED 2008: 297-300 |
| 6 | | Santhosh Coimbatore Vaidyanathan,
Amit Mangesh Brahme,
Sukumar Jairam:
Techniques for Early Package Closure in System-in-Packages.
ISQED 2008: 608-613 |
| 5 | | Sukumar Jairam,
Navakanta Bhat:
GyroCompiler: A Soft IP Model Synthesis and Analysis Framework for Design of MEMS Based Gyroscopes.
VLSI Design 2008: 589-594 |
| 2007 |
|---|
| 4 | | Sankar P. Debnath,
Ganesh P. Kumar,
Sukumar Jairam:
Calibration Based Methods for Substrate Modeling and Noise Analysis for Mixed-Signal SoCsc.
VLSI Design 2007: 887-892 |
| 2006 |
|---|
| 3 | | Snehashis Roy,
Sukumar Jairam,
H. Udayakumar:
A Methodology for Switching Activity Based IO Powerpad Optimisation.
VLSI Design 2006: 794-797 |
| 2005 |
|---|
| 2 | | Sankar P. Debnath,
Sukumar Jairam,
H. Udayakumar:
A Methodology for Fast Vector Based Power Supply and Substrate Noise Analyses.
VLSI Design 2005: 808-811 |
| 2004 |
|---|
| 1 | | Sukumar Jairam,
C. Venkatesh,
Navakanta Bhat,
Shyam Singh,
Rudra Pratap:
A Quasi Static Model for a Simply Supported Beam in a Circuit Simulation Framework.
VLSI Design 2004: 642-645 |
Data released under the ODC-BY 1.0 license — See also our legal information page