 | 2011 |
|---|
| 9 |       | Marius Grannæs,
Magnus Jahre,
Lasse Natvig:
Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy.
ARCS 2011: 135-146 |
| 8 | | Magnus Jahre,
Lasse Natvig:
A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors.
T. HiPEAC 4: 1-20 (2011) |
| 2010 |
|---|
| 7 | | Marius Grannæs,
Magnus Jahre,
Lasse Natvig:
Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching.
HiPEAC 2010: 247-261 |
| 6 | | Magnus Jahre,
Marius Grannæs,
Lasse Natvig:
DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems.
HiPEAC 2010: 292-306 |
| 5 | | Magnus Jahre,
Lasse Natvig:
Computational Computer Architecture Research at NTNU.
ERCIM News 2010(81): (2010) |
| 2009 |
|---|
| 4 | | Magnus Jahre,
Lasse Natvig:
A light-weight fairness mechanism for chip multiprocessor memory systems.
Conf. Computing Frontiers 2009: 1-10 |
| 3 | | Magnus Jahre,
Marius Grannæs,
Lasse Natvig:
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures.
HPCC 2009: 622-629 |
| 2 | | Guttorm Sindre,
Lasse Natvig,
Magnus Jahre:
Experimental Validation of the Learning Effect for a Pedagogical Game on Computer Fundamentals.
IEEE Trans. Education 52(1): 10-18 (2009) |
| 2008 |
|---|
| 1 | | Marius Grannæs,
Magnus Jahre,
Lasse Natvig:
Low-cost open-page prefetch scheduling in chip multiprocessors.
ICCD 2008: 390-396 |
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