 | 2012 |
|---|
| 7 |       | Wasim Hussain,
Shah M. Jahinuzzaman:
A read-decoupled gated-ground SRAM architecture for low-power embedded memories.
Integration 45(3): 229-236 (2012) |
| 2011 |
|---|
| 6 | | Wasim Hussain,
Shah M. Jahinuzzaman:
A 7T SRAM bit-cell for low-power embedded memories.
ACM Great Lakes Symposium on VLSI 2011: 121-126 |
| 5 | | Mohammad Sharifkhani,
E. Rahiminejad,
Shah M. Jahinuzzaman,
Manoj Sachdev:
A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs.
IEEE Trans. VLSI Syst. 19(5): 883-894 (2011) |
| 2010 |
|---|
| 4 | | Hourieh Attarzadeh,
Mohammad Sharifkhani,
Shah M. Jahinuzzaman:
A scalable offset-cancelled current/voltage sense amplifier.
ISCAS 2010: 3853-3856 |
| 2009 |
|---|
| 3 | | Shah M. Jahinuzzaman,
Mohammad Sharifkhani,
Manoj Sachdev:
An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs.
IEEE Trans. VLSI Syst. 17(9): 1187-1195 (2009) |
| 2008 |
|---|
| 2 | | Shah M. Jahinuzzaman,
Mohammad Sharifkhani,
Manoj Sachdev:
Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model.
ISQED 2008: 207-212 |
| 2006 |
|---|
| 1 | | Mohammad Sharifkhani,
Shah M. Jahinuzzaman,
Manoj Sachdev:
Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests.
MTDT 2006: 55-64 |
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