 | 2012 |
| 20 |  | Marzieh Morshedzadeh Morshedzadeh,
Ali Jahanian:
Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage.
ACM Great Lakes Symposium on VLSI 2012: 303-306 |
| 19 |  | Sirvan Khalighi,
Somayeh Maabi,
Mercedeh Sanjabi,
Ali Jahanian:
Landmark-based Car Navigation with Overtake Capability in Multi-agent Environments.
ICAART (2) 2012: 234-239 |
| 2011 |
| 18 |  | Mehdi Alipour,
Mohammad Haji Seyed Javadi,
Ali Jahanian:
Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology.
ACM Great Lakes Symposium on VLSI 2011: 49-54 |
| 17 |  | Behzad Salami,
Morteza Saheb Zamani,
Ali Jahanian:
VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs.
DSD 2011: 81-87 |
| 16 |  | Adel Dokhanchi,
Ali Jahanian,
Esfandiar Mehrshahi,
M. Taghi Teimoori:
Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks Usage.
ISVLSI 2011: 1-6 |
| 15 |  | Zohre Mohammadi-Arfa,
Ali Jahanian:
A Hybrid RF/Metal Clock Routing Algorithm to Improve Clock Delay and Routing Congestion.
ISVLSI 2011: 138-143 |
| 14 |  | Ali Jahanian,
Morteza Saheb Zamani,
Hamid Safizadeh:
Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology.
Integration 44(2): 123-135 (2011) |
| 2010 |
| 13 |  | Ali Jahanian,
Morteza Saheb Zamani:
Early Buffer Planning with Congestion Control Using Buffer Requirement Map.
Journal of Circuits, Systems, and Computers 19(5): 949-973 (2010) |
| 2009 |
| 12 |  | Ali Jahanian,
Morteza Saheb Zamani:
Improved performance and yield with chip master planning design methodology.
ACM Great Lakes Symposium on VLSI 2009: 185-190 |
| 11 |  | Naser MohammadZadeh,
Minoo Mirsaeedi,
Ali Jahanian,
Morteza Saheb Zamani:
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network.
DATE 2009: 833-838 |
| 10 |  | Mercedeh Sanjabi,
Somayeh Maabi,
Zahra Esmaeili,
Ali Jahanian,
Sirvan Khalighi:
A Landmark-Based Navigation System for High Speed Cars in the Roads with Branches.
I. J. Information Acquisition 6(3): 193-202 (2009) |
| 2008 |
| 9 |  | Ali Jahanian,
Morteza Saheb Zamani:
Performance and Timing Yield Enhancement using Highway-on-Chip Planning.
DSD 2008: 165-172 |
| 8 |  | Adel Dokhanchi,
Mostafa Rezvani,
Ali Jahanian,
Morteza Saheb Zamani:
Performance Improvement of Physical Retiming with Shortcut Insertion.
ISVLSI 2008: 215-220 |
| 7 |  | Ali Jahanian,
Morteza Saheb Zamani:
Using metro-on-chip in physical design flow for congestion and routability improvement.
Microelectronics Journal 39(2): 261-274 (2008) |
| 2007 |
| 6 |  | Ali Jahanian,
Morteza Saheb Zamani:
Improved timing closure by early buffer planning in floor-placement design flow.
ACM Great Lakes Symposium on VLSI 2007: 558-563 |
| 5 |  | Mehdi Saeedi,
Morteza Saheb Zamani,
Ali Jahanian:
Evaluation, prediction and reduction of routing congestion.
Microelectronics Journal 38(8-9): 942-958 (2007) |
| 2006 |
| 4 |  | Mehdi Saeedi,
Morteza Saheb Zamani,
Ali Jahanian:
Prediction and reduction of routing congestion.
ISPD 2006: 72-77 |
| 3 |  | Ali Jahanian,
Morteza Saheb Zamani:
Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits.
ISVLSI 2006: 411-415 |
| 2005 |
| 2 |  | Hamid Safizadeh,
Hamid Noori,
Mehdi Sedighi,
Ali Jahanian,
Neda Zolfaghari:
Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms.
DSD 2005: 227-230 |
| 2004 |
| 1 |  | Mohammad K. Akbari,
Ali Jahanian,
Mohsen Naderi,
Bahman Javadi:
Area Efficient, Low Power and Robust Design for Add-Compare-Select Units.
DSD 2004: 611-614 |