 | 2011 |
| 13 |  | Desheng Ma,
Fa Foster Dai,
Richard C. Jaeger,
J. David Irwin:
An X- and Ku-Band Wideband Recursive Receiver MMIC With Gain-Reuse.
J. Solid-State Circuits 46(3): 562-571 (2011) |
| 2010 |
| 12 |  | Xueyang Geng,
Fa Foster Dai,
J. David Irwin,
Richard C. Jaeger:
An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC.
J. Solid-State Circuits 45(2): 300-313 (2010) |
| 11 |  | Jianjun Yu,
Fa Foster Dai,
Richard C. Jaeger:
A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 μħbox m CMOS Technology.
J. Solid-State Circuits 45(4): 830-842 (2010) |
| 10 |  | Xueyang Geng,
Fa Foster Dai,
J. David Irwin,
Richard C. Jaeger:
24-Bit 5.0 GHz Direct Digital Synthesizer RFIC With Direct Digital Modulations in 0.13 μ m SiGe BiCMOS Technology.
J. Solid-State Circuits 45(5): 944-954 (2010) |
| 2009 |
| 9 |  | Dayu Yang,
Foster F. Dai,
Weining Ni,
Yin Shi,
Richard C. Jaeger:
Delta-Sigma Modulation for Direct Digital Frequency Synthesis.
IEEE Trans. VLSI Syst. 17(6): 793-802 (2009) |
| 2006 |
| 8 |  | Yuan Yao,
Xuefeng Yu,
Foster F. Dai,
Richard C. Jaeger:
A 12-bit current steering DAC for cryogenic applications.
ISCAS 2006 |
| 7 |  | Oimins Xu,
Xueqing Hu,
Pens Gao,
Jun Yan,
Yin Shi,
Foster F. Dai,
Richard C. Jaeger:
A direct-conversion mixer with DC-offset cancellation for IEEE 802.11a WLAN receiver.
ISCAS 2006 |
| 2005 |
| 6 |  | Vasanth Kakani,
Foster F. Dai,
Richard C. Jaeger:
An high speed integrated equalizer for dispersion compensation in 10Gb/s fiber networks.
ISCAS (2) 2005: 1178-1181 |
| 5 |  | Foster F. Dai,
Shengfang Wei,
Richard C. Jaeger:
Integrated blind electronic equalizer for fiber dispersion compensation.
ISCAS (6) 2005: 5750-5753 |
| 2004 |
| 4 |  | Malinky Ghosh,
Lakshmi S. J. Chimakurthy,
Foster F. Dai,
Richard C. Jaeger:
A novel DDS architecture using nonlinear ROM addressing with improved compression ratio and quantisation noise.
ISCAS (2) 2004: 705-708 |
| 3 |  | Vasanth Kakani,
Foster F. Dai,
Richard C. Jaeger:
Delay analysis and optimal biasing for high speed low power Current Mode Logic circuits.
ISCAS (2) 2004: 869-872 |
| 1986 |
| 2 |  | Richard C. Jaeger:
Computer-Aided Design of One-Dimensional MOSFET Impurity Profiles.
IEEE Trans. on CAD of Integrated Circuits and Systems 5(1): 198-203 (1986) |
| 1983 |
| 1 |  | Richard C. Jaeger,
Fritz H. Gaensslen,
Sherra E. Diehl:
An Efficient Numerical Algorithm for Simulation of MOS Capacitance.
IEEE Trans. on CAD of Integrated Circuits and Systems 2(2): 111-116 (1983) |