 | 2012 |
| 20 |  | Mahesh Poolakkaparambil,
Jimson Mathew,
Abusaleh M. Jabir,
Saraju P. Mohanty:
Low complexity cross parity codes for multiple and random bit error correction.
ISQED 2012: 57-62 |
| 2011 |
| 19 |  | Mahesh Poolakkaparambil,
Jimson Mathew,
Abusaleh M. Jabir,
Dhiraj K. Pradhan:
A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields.
ECCTD 2011: 600-603 |
| 18 |  | Mahesh Poolakkaparambil,
Jimson Mathew,
Abusaleh M. Jabir,
Dhiraj K. Pradhan,
Saraju P. Mohanty:
BCH code based multiple bit error correction in finite field multiplier circuits.
ISQED 2011: 615-620 |
| 2010 |
| 17 |  | Jimson Mathew,
Hafizur Rahaman,
Abusaleh M. Jabir,
Saraju P. Mohanty,
Dhiraj K. Pradhan:
On the design of different concurrent EDC schemes for S-Box and GF(p).
ISQED 2010: 211-218 |
| 16 |  | Jimson Mathew,
Savita Banerjee,
Hafizur Rahaman,
Dhiraj K. Pradhan,
Saraju P. Mohanty,
Abusaleh M. Jabir:
On the synthesis of attack tolerant cryptographic hardware.
VLSI-SoC 2010: 286-291 |
| 15 |  | Jimson Mathew,
Abusaleh M. Jabir,
Ashutosh Kumar Singh,
Hafizur Rahaman,
Dhiraj K. Pradhan:
A Galois field-based logic synthesis with testability.
IET Computers & Digital Techniques 4(4): 263-273 (2010) |
| 14 |  | Hafizur Rahaman,
Jimson Mathew,
Abusaleh M. Jabir,
Dhiraj K. Pradhan:
Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability.
IET Computers & Digital Techniques 4(5): 428-437 (2010) |
| 2009 |
| 13 |  | Hafizur Rahaman,
Jimson Mathew,
Abusaleh M. Jabir,
Dhiraj K. Pradhan:
C-testable S-box implementation for secure advanced encryption standard.
IOLTS 2009: 210-211 |
| 12 |  | Jimson Mathew,
Abusaleh M. Jabir,
Hafizur Rahaman,
Dhiraj K. Pradhan:
Single error correctable bit parallel multipliers over GF(2m).
IET Computers & Digital Techniques 3(3): 281-288 (2009) |
| 2008 |
| 11 |  | Jimson Mathew,
Abusaleh M. Jabir,
Dhiraj K. Pradhan:
Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection.
IOLTS 2008: 16-21 |
| 10 |  | Jimson Mathew,
Jawar Singh,
Abusaleh M. Jabir,
Mohammad Hosseinabady,
Dhiraj K. Pradhan:
Fault tolerant bit parallel finite field multipliers using LDPC codes.
ISCAS 2008: 1684-1687 |
| 9 |  | Jimson Mathew,
Costas Argyrides,
Abusaleh M. Jabir,
Hafizur Rahaman,
Dhiraj K. Pradhan:
Single Error Correcting Finite Field Multipliers Over GF(2m).
VLSI Design 2008: 33-38 |
| 8 |  | Jimson Mathew,
Hafizur Rahaman,
Ashutosh Kumar Singh,
Abusaleh M. Jabir,
Dhiraj K. Pradhan:
A Galois Field Based Logic Synthesis Approach with Testability.
VLSI Design 2008: 629-634 |
| 7 |  | Hafizur Rahaman,
Jimson Mathew,
Dhiraj K. Pradhan,
Abusaleh M. Jabir:
C-testable bit parallel multipliers over GF(2m).
ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
| 6 |  | Hafizur Rahaman,
Jimson Mathew,
Dhiraj K. Pradhan,
Abusaleh M. Jabir:
Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m).
IEEE Trans. Computers 57(9): 1289-1294 (2008) |
| 5 |  | Abusaleh M. Jabir,
Dhiraj K. Pradhan,
Jimson Mathew:
GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 698-711 (2008) |
| 2007 |
| 4 |  | Abusaleh M. Jabir,
Dhiraj K. Pradhan:
A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields.
IEEE Trans. Computers 56(8): 1119-1132 (2007) |
| 3 |  | Abusaleh M. Jabir,
Dhiraj K. Pradhan,
T. L. Rajaprabhu,
Ashutosh Kumar Singh:
A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation.
IEEE Trans. Computers 56(8): 1133-1145 (2007) |
| 2006 |
| 2 |  | Abusaleh M. Jabir,
Dhiraj K. Pradhan,
Jimson Mathew:
An efficient technique for synthesis and optimization of polynomials in GF(2m).
ICCAD 2006: 151-157 |
| 2004 |
| 1 |  | Abusaleh M. Jabir,
Dhiraj K. Pradhan:
MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions.
DATE 2004: 1388-1389 |