 | 2011 |
|---|
| 13 |       | Saeid Gorgin,
Ghassem Jaberipur:
A Family of High Radix Signed Digit Adders.
IEEE Symposium on Computer Arithmetic 2011: 112-120 |
| 12 | | Amir Kaivani,
Ghassem Jaberipur:
Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture.
Comput. J. 54(11): 1798-1809 (2011) |
| 11 | | Amir Kaivani,
Adel Hosseiny,
Ghassem Jaberipur:
Improving the speed of decimal division.
IET Computers & Digital Techniques 5(5): 393-404 (2011) |
| 2010 |
|---|
| 10 | | Ghassem Jaberipur,
Saeid Gorgin:
An improved maximally redundant signed digit adder.
Computers & Electrical Engineering 36(3): 491-502 (2010) |
| 9 | | Ghassem Jaberipur,
Behrooz Parhami,
Saeid Gorgin:
Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value.
IEEE Trans. Computers 59(5): 694-706 (2010) |
| 8 | | Amir Kaivani,
Ghassem Jaberipur:
Fully redundant decimal addition and subtraction using stored-unibit encoding.
Integration 43(1): 34-41 (2010) |
| 2009 |
|---|
| 7 | | Saeid Gorgin,
Ghassem Jaberipur:
Fully Redundant Decimal Arithmetic.
IEEE Symposium on Computer Arithmetic 2009: 145-152 |
| 6 | | Ghassem Jaberipur,
Behrooz Parhami:
Unified Approach to the Design of Modulo-(2n +/- 1) Adders Based on Signed-LSB Representation of Residues.
IEEE Symposium on Computer Arithmetic 2009: 57-64 |
| 5 | | Ghassem Jaberipur,
Amir Kaivani:
Improving the Speed of Parallel Decimal Multiplication.
IEEE Trans. Computers 58(11): 1539-1552 (2009) |
| 4 | | Saeid Gorgin,
Ghassem Jaberipur:
A fully redundant decimal adder and its application in parallel decimal multipliers.
Microelectronics Journal 40(10): 1471-1481 (2009) |
| 2008 |
|---|
| 3 | | Ghassem Jaberipur,
Behrooz Parhami:
Constant-time addition with hybrid-redundant numbers: Theory and implementations.
Integration 41(1): 49-64 (2008) |
| 2007 |
|---|
| 2 | | Ghassem Jaberipur,
Amir Kaivani:
Binary-coded decimal digit multipliers.
IET Computers & Digital Techniques 1(4): 377-381 (2007) |
| 2006 |
|---|
| 1 | | Ghassem Jaberipur,
Behrooz Parhami,
Mohammad Ghodsi:
An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding.
VLSI Signal Processing 42(2): 149-158 (2006) |
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